Routed vs signal lenght
nachodizz990 , 08-16-2016, 05:08 PM
Hi all, i sensed that in my project the signal lenghts doesn´t match the routed lenghts and in the OpenRex DDR_BANKS they match
- What is the difference, i never realized on this!
Thank you in advance !
- What is the difference, i never realized on this!
Thank you in advance !
mairomaster , 08-17-2016, 02:13 AM
A small difference is OK. The routed one is calculating by simply adding up the lengths of all track segments/via parts. The electrical one considers the exact flow of the signal - for example if you have track segments in a pad, the signal flows by the shortest cut in the pad since it is all copper - it doesn't need to follow the track anymore. For the length matching rules the signal length is considered (since Altium 16), so you don't need to worry too much about the routed length.
Big difference might mean you have duplicate track segments.
Big difference might mean you have duplicate track segments.
nachodizz990 , 08-19-2016, 09:55 PM
Very good info , you solved in one strike all the doubts i had with this aspect of altium lenghts so thank you.
About duplicate tracks i reviewed all and all the nets are clean
Why can be the the problem if i have, by example, 860 routed and 50 mil diference with signal lenght
About duplicate tracks i reviewed all and all the nets are clean
Why can be the the problem if i have, by example, 860 routed and 50 mil diference with signal lenght
mairomaster , 08-20-2016, 05:48 AM
50 mil is a lot, so either there should be an obvious reason or something dodgy is going on.
If it is a simple point to point signal (DDR DQ for example) I can't see how this could happen. Such big differences I've had in the past with either duplicate segment or several short segments in a pad, done by mistake. But all of those can be noticed when you highlight the track segments and inspect closely. Also remember that the reading is only valid for point to point signals, it doesn't work with tree branch, when you have termination resistors or series resistors in the signal. For those cases you need to use xSignals.
I often have differences like 1mil, which is normal since the two algorithms work differently.
If it is a simple point to point signal (DDR DQ for example) I can't see how this could happen. Such big differences I've had in the past with either duplicate segment or several short segments in a pad, done by mistake. But all of those can be noticed when you highlight the track segments and inspect closely. Also remember that the reading is only valid for point to point signals, it doesn't work with tree branch, when you have termination resistors or series resistors in the signal. For those cases you need to use xSignals.
I often have differences like 1mil, which is normal since the two algorithms work differently.
nachodizz990 , 08-22-2016, 11:46 AM
@mairomaster, check at this
https://drive.google.com/open?id=0B8...0FZcWhKaTNrc0E
There are 3 pcb docs
1- From Top Vias To Mem 1 :
Routed lenght matched Without xSignals ( with the nets panel) and routed under 3 mil tolerance
2- Mem 1 to Mem2
Routed lenght matched Without xSignals ( with the nets panel) and routed under 3 mil tolerance
If i enable xsignals, it measures this stage the same that the nets panel
3- I Pasted the previous 2 inside this pcbdoc
This is the entire flyby chain, the problem is that now there is 37mil tolerance in the nets panel routed lenght WTF!!
The maximum tolerance desviation after pasting should not be more than 3 mil x 2 = 6 mil
I supose that the vias to Memory 1 lenght will be fine when i route the signals from sov to memory 1....
About the Byte lanes now the routed and signal lenghts are the same, i had duplicate xsignal clases , i cleaned the xsignal stuff and now it´s fine
https://drive.google.com/open?id=0B8...0FZcWhKaTNrc0E
There are 3 pcb docs
1- From Top Vias To Mem 1 :
Routed lenght matched Without xSignals ( with the nets panel) and routed under 3 mil tolerance
2- Mem 1 to Mem2
Routed lenght matched Without xSignals ( with the nets panel) and routed under 3 mil tolerance
If i enable xsignals, it measures this stage the same that the nets panel
3- I Pasted the previous 2 inside this pcbdoc
This is the entire flyby chain, the problem is that now there is 37mil tolerance in the nets panel routed lenght WTF!!
The maximum tolerance desviation after pasting should not be more than 3 mil x 2 = 6 mil
I supose that the vias to Memory 1 lenght will be fine when i route the signals from sov to memory 1....
About the Byte lanes now the routed and signal lenghts are the same, i had duplicate xsignal clases , i cleaned the xsignal stuff and now it´s fine
mairomaster , 08-22-2016, 05:44 PM
For this situation I will setup xSignals - one part for the signals between the two DDR chips and another part from the FPGA to the first DDR chip.
robertferanec , 08-23-2016, 08:21 AM
It should be FPGA to the first memory chip and FPGA to the second memory chip. When I played with xSignals I thought, that it cold be set as you are suggesting (using length between memory chips), but the length matching would not be correct e.g. Altium would be considering a part of track between the first memory chip and closest VIA which may not be the same for all the pins. It's not possible to spot this length difference so easily, so you need to imagine what parts of tracks are considered when you do memory - memory length matching comparing to the FPGA to second memory length matching and then you will know what I mean. If it's not clear, I will draw it.
nachodizz990 , 08-23-2016, 01:46 PM
Yes , i understand, thank you soo much, the problem is on the layer 1 breakout and vias but i will solve as follows.
- Knowing that xsignals it´s measuring fine the memory 1 to memory 2 stage , when i route the ARM DDR3 signals to the first memory chip (TOP VIAS), I will correct implicitly this situation
- Knowing that xsignals it´s measuring fine the memory 1 to memory 2 stage , when i route the ARM DDR3 signals to the first memory chip (TOP VIAS), I will correct implicitly this situation
robertferanec , 08-23-2016, 03:05 PM
@nachodizz990 what I tried to explain in my previous post is, that xSignal distance between memory 1 and memory 2 is irrelevant. You want to setup xSignals between FPGA and first memory chip and xSignals between FPGA and second memory chip.
Comments:
robertferanec, 08-24-2016, 06:40 AM
No. If distance from FPGA to MEM1 is length matched and distance from FPGA to MEM2 is length matched, it doesn't mean that MEM1 to MEM2 is the same There is a piece of track between MEM1 and cloesest VIA which plays big role in this.
nachodizz990 , 09-02-2016, 08:51 AM
Hi @robertferanec, i finished all DDR supply, now i want to go connecting the SoC to the fly.by, can you xplain me that piece of track xD i want to perfectly lenght match the address ctrl and cmd groups
robertferanec , 09-05-2016, 10:00 AM
It's very individual between chips, so the best is read a design guide for the particular chip. However, basically this is how it normally works:
- clock is longest
- addr/cmd/ctl are a little bit shorter
What you want to achieve is, that addr/cmd/ctl signals arrive at the same time from FPGA to a particular memory chip, so you need to do length matching between FPGA <-> MEM1, and then also you need to do length matching between FPGA <-> MEM2. If you are not sure, you can always measure lengths on available boards with Fly-by memory layouts and check how other people did that. You can have a look at our OpenRex board or you can have a look at memory module layout examples at JEDEC website (you have to register, but you can download reference designs of different memory modules for free): DDR, DDR2 and DDR3 – PCB layout examples
- clock is longest
- addr/cmd/ctl are a little bit shorter
What you want to achieve is, that addr/cmd/ctl signals arrive at the same time from FPGA to a particular memory chip, so you need to do length matching between FPGA <-> MEM1, and then also you need to do length matching between FPGA <-> MEM2. If you are not sure, you can always measure lengths on available boards with Fly-by memory layouts and check how other people did that. You can have a look at our OpenRex board or you can have a look at memory module layout examples at JEDEC website (you have to register, but you can download reference designs of different memory modules for free): DDR, DDR2 and DDR3 – PCB layout examples
nachodizz990 , 09-05-2016, 11:03 AM
Thank You @robertferanec, i viewed the Open Rex and the layout it´s done exactly the same what i´m doing so now i understand what you mean!
I readed JESD79-3E and all Xilinx , Altera, Micron, NXP, TI notes about DDR xD
I routed the fly by first and matched mem1 to mem2 more or les but i will adjust when i do the complete layout
On the OpenRex The lines were routed by order (first soc - bottom and then to top fly-by vias and mem1-> mem2->mem3->mem4
On the OpenRex All the stages are matched to 1 mil (so fine) and knowing that altium computes the layer you enter and exit the via i suppose that the skew it´s minimum
I ported Open Re to xSignals to check what you say and now i perfectly understand it
I know that:
-The clock should have the same lenght that addr_cmd_ctrl (+/- 25 ps) i supose that clock should be the longest within this tolerance for the first memory so that when clk arrives, all the signals are "quiet" (sample and hold stuff and time budget)
I will make the clock the longest in the address_ctrl_cmd group before the memory 1 so that from mem 1 to mem 2 i dont have to worry about the clock to be the fastest
-The clk and addr_cmd_ctrl lenght should not be shortest than the dqs because the controller is not able to do the calibration under this circunstances (excepting in some i.Mx controllers that allow it to be quite shortest)
-The dqs, dq dqm etc should have the same leght (+/- 10 ps) and the dqs lenght should be centered between the longest and shorthest dq/dqm
What i dont undestand is this altera doc about tdqss
I´m finishing the SoC decoupling
When i finish this board i will send you the project if you want to take a look an then i will start a cheap i.MX7 $14 Soc based pcb
(There are writting the documentation on NXP but the available docs are enought to get started i also ordered a arrow i.mx7 red board)
I like so much the cortex m4 inside
I readed JESD79-3E and all Xilinx , Altera, Micron, NXP, TI notes about DDR xD
I routed the fly by first and matched mem1 to mem2 more or les but i will adjust when i do the complete layout
On the OpenRex The lines were routed by order (first soc - bottom and then to top fly-by vias and mem1-> mem2->mem3->mem4
On the OpenRex All the stages are matched to 1 mil (so fine) and knowing that altium computes the layer you enter and exit the via i suppose that the skew it´s minimum
I ported Open Re to xSignals to check what you say and now i perfectly understand it
I know that:
-The clock should have the same lenght that addr_cmd_ctrl (+/- 25 ps) i supose that clock should be the longest within this tolerance for the first memory so that when clk arrives, all the signals are "quiet" (sample and hold stuff and time budget)
I will make the clock the longest in the address_ctrl_cmd group before the memory 1 so that from mem 1 to mem 2 i dont have to worry about the clock to be the fastest
-The clk and addr_cmd_ctrl lenght should not be shortest than the dqs because the controller is not able to do the calibration under this circunstances (excepting in some i.Mx controllers that allow it to be quite shortest)
-The dqs, dq dqm etc should have the same leght (+/- 10 ps) and the dqs lenght should be centered between the longest and shorthest dq/dqm
What i dont undestand is this altera doc about tdqss
I´m finishing the SoC decoupling
When i finish this board i will send you the project if you want to take a look an then i will start a cheap i.MX7 $14 Soc based pcb
(There are writting the documentation on NXP but the available docs are enought to get started i also ordered a arrow i.mx7 red board)I like so much the cortex m4 inside
robertferanec , 09-05-2016, 06:06 PM
- that means, that CLK distance from FPGA to memory chip is longer than length of DQS (it has to be valid for every memory chip). This is normally not a problem ... only in cases when people try to place DRAM chips rotated by 180 Degrees (closer with ADDR/CMD/CTRL pins to the FPGA and placing data pins further from the FPGA - that could be a problem).
- that means, that all DQS signals should be similar or in a kind of tolerance. Using different words, there must not be a huge difference in the length between the shortest and the longest DQS between data banks e.g. you may not have a data bank routed with 1cm tracks and another data bank routed with 15cm tracks. Again, this is normally not a problem (usually you have FPGA placed in the middle between memory chips). Only if you would like to place memory chips extremely asymmetrically (you move all the memory chips to the left or right side of the FPGA), then it could be a problem.
- that means, that all DQS signals should be similar or in a kind of tolerance. Using different words, there must not be a huge difference in the length between the shortest and the longest DQS between data banks e.g. you may not have a data bank routed with 1cm tracks and another data bank routed with 15cm tracks. Again, this is normally not a problem (usually you have FPGA placed in the middle between memory chips). Only if you would like to place memory chips extremely asymmetrically (you move all the memory chips to the left or right side of the FPGA), then it could be a problem.
nachodizz990 , 09-05-2016, 08:47 PM
Thank you @robertferanec for yor efforts explainig me all this stuff I am REALLY grateful!!
I routed T branch (with 2 memories) succesfully two times but i moved to Fly By because the integrity is much better, and just in case one day i need to place 4 memories i want to be proficient on fly by because i hate dual t- branch (4 memories) and also single xD
I dont like to perform strange component placements, i like nice boards but i ever respect the better signal distribution
In the JESD 79 i read that for fully compilance the dqs and clk_address_cmd should be very similar but this is imposible on this boards and i think that it applies for pc motherboard for fully compilance (just in case It´s better to look at the controller datasheet)
After reading Jesd 79 my conclusion is that the most difficult interfaces should be the dual fly- by topology with LPDDR and multi die memories (high capacitance)
This Cyclone SoC board it´s the most difficult layout i ever made because the io balls cant be worst distributed :@ I think that they expect you to use 20 layer or something similar xD
I routed T branch (with 2 memories) succesfully two times but i moved to Fly By because the integrity is much better, and just in case one day i need to place 4 memories i want to be proficient on fly by because i hate dual t- branch (4 memories) and also single xD
I dont like to perform strange component placements, i like nice boards but i ever respect the better signal distribution
In the JESD 79 i read that for fully compilance the dqs and clk_address_cmd should be very similar but this is imposible on this boards and i think that it applies for pc motherboard for fully compilance (just in case It´s better to look at the controller datasheet)
After reading Jesd 79 my conclusion is that the most difficult interfaces should be the dual fly- by topology with LPDDR and multi die memories (high capacitance)
This Cyclone SoC board it´s the most difficult layout i ever made because the io balls cant be worst distributed :@ I think that they expect you to use 20 layer or something similar xD
robertferanec , 09-06-2016, 07:06 AM
This Cyclone SoC board it´s the most difficult layout i ever made because the io balls cant be worst distributed :@ I think that they expect you to use 20 layer or something similar xD
I have seen some 24 layer reference boards with a few tracks per layer .... I think it was Altera 
Comments:
nachodizz990, 09-07-2016, 09:41 AM
The worst aspect it´s the decoupling caps BOM Also one aspect i dont like is to have routing layer almost empty, one pcb manufacturer toldme that it´s important to have balanced cooper areas
milos.stankovic , 07-19-2019, 10:07 AM
Hi!
I have similar problem with my current design. I cannot understand how Routed Length can be smaller than Signal Length. There are small overlaps of the segments that make one track. That is why I expected that Signal length is somewhat smaller since it should not calculate this small overlaps more then ones. Here is how it looks like on the picture below. If I try deliberately to add segments on top of each other I get Routed Length getting bigger, but Signal Length remains the same and that is ok, that is how Altium's algorithm works. Once more, I cannot see how situation on the picture is possible.
Rregards,
Milos
I have similar problem with my current design. I cannot understand how Routed Length can be smaller than Signal Length. There are small overlaps of the segments that make one track. That is why I expected that Signal length is somewhat smaller since it should not calculate this small overlaps more then ones. Here is how it looks like on the picture below. If I try deliberately to add segments on top of each other I get Routed Length getting bigger, but Signal Length remains the same and that is ok, that is how Altium's algorithm works. Once more, I cannot see how situation on the picture is possible.
Rregards,
Milos
milos.stankovic , 07-22-2019, 12:44 AM
Hi!
I think I know what causes the difference between Routed Length and Signal Length. I have via in pad. That is what makes the problem.
Regards,
Milos
I think I know what causes the difference between Routed Length and Signal Length. I have via in pad. That is what makes the problem.
Regards,
Milos
robertferanec , 07-24-2019, 07:08 AM
Interesting. Thank you for sharing.
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