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Forum / Altium Designer / AREA clearance rule

AREA clearance rule

gabrielcuellar , 08-31-2016, 01:38 PM

Hi all.
I donÂ´t know how set a rule to realize the way of nets in a determinated area like a perimeter of a component for example I see the rule, in the video

Altium Tutorial - Smaller clearance under BGA or Footprint

https://www.youtube.com/watch?v=B8wQVrPKTSw

When you are doing layout, sometimes you may want to use a special rule in a specific area, for example if you have a BGA with a very small pitch, which requ...

but this only works if only this rule is the one.
For example in my pcb the first rule is a clarance all-all 12 mil and then all nets are marking with violation around the component but because between it`s pad the distance is 7mil.
Then I apply the rule of video but this violations not disappears. I been searching and I found something like a define a room but I donÂ´t understand then, how link this in the query of the clearance rules, I need some rule like a area where allow a clearance < 12 mil. I donÂ´t know how to do that. Some idea for this problem? Thanks

robertferanec , 08-31-2016, 02:09 PM

Hello @gabrielcuellar. Please, can you run DRC (Tools -> Design Rule Check -> Run Design rule Check) and then when you are in the PCB, click on the "PCB" button in the right bottom corner, select "PCB Rules and Violations". Please, browse the Violations and post a screenshot of the PCB Rules and Violations which you think are related to the problem.

gabrielcuellar , 08-31-2016, 02:39 PM

Thank you for your reply Robert. I think the problem itÂ´s in the first violation in the image for example one of many, there are so many violations, but I donÂ´t care, for the moment.

robertferanec , 08-31-2016, 02:51 PM

Please, find and select in the PCB Rules and Violations window only the U5 rule. Just to be 100% the violations are generated by the rule.

gabrielcuellar , 09-01-2016, 06:18 AM

I run the DRC again but the violation over the nets around the component U5 disappear. But I try move the track and the violation appears again. The violation are by clearance between nets and between nets and pads of U5, I don`t know how show you only the violation over U5, but this screenshots help.

robertferanec , 09-01-2016, 07:13 AM

Can you post a screenshot of the whole U5 rule? Did you try to put there only the one footprint or you are trying to apply the rule on more footprints? It looks to me like in the rule you have something like "HasFootprint('STM_LQFP100_N', 'SOIC ....'". Hmm, I have never seen a rule like that, I would use OR between more footprints e.g. HasFootprint('XXX') OR HasFootprint('XXX'), .... Could you try it with one footprint only, if it helps?

gabrielcuellar , 09-01-2016, 07:56 AM

Yes, of course, I just think in this form to concatenate the footprints in one query, also try follow your advice but this have the same effect.

robertferanec , 09-01-2016, 08:07 AM

Hmm, now, I do not really know

Did you try the "Test queries" button?

gabrielcuellar , 09-01-2016, 08:48 AM

Yes, I do, and no error but now I put the syntax HasFootprint('STM-LQFP100_N')OR HasFootprint('SOIC-28') to discard some error in the if it existed.
Is there any rule affecting the nets of the rooms?
How did I can apply?

robertferanec , 09-01-2016, 09:51 AM

Ok, I tested it on my AD 16 and it works just fine. Here are the screenshots:

robertferanec , 09-01-2016, 09:55 AM

I think, I know what the problem can be. In your last screenshot it looks almost right ... the errors seems to me to be between TRACKS in the area under footprint. The rule is between the footprint and anything on layer 1, but it is not a rule for TRACK to TRACK under the footprint. For this, you may want to specify AREA (instead of using HasFootprint) or make the tracks thinner.

gabrielcuellar , 09-01-2016, 10:01 AM

Yes, that is the problem between "Tracks". I was wrong to write "Nets" up to the post.

robertferanec , 09-01-2016, 10:09 AM

Yes, try to create ROOM (Design -> Rooms -> Place Rectangular Room) and then Create a clearance rule which applies to the ROOM (I personally try to avoid using ROOMS as you need to make then an exception when you will be porting schematic, otherwise it will want to remove it - or it used to, maybe in AD16 they improved it)

robertferanec , 09-01-2016, 10:25 AM

Here is the result (Don't forget, you need to disable the ROOM Rule created automatically: Design -> Rules -> Design Rules -> Placement -> Room Definition -> ROOMNAME and Uncheck "Enabled"). You can rename a ROOM, just double click on it.