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angelsix , 10-21-2015, 10:57 AM

There is something very wrong with the length matching rules.

I have 2 totally different diff pairs, with different net names and different net classes.

Instead of PCIE_TX_P and _N matching their own lengths, they try to match an arbitrary other diff pair called SSD_TX2.

No idea why.

angelsix , 10-21-2015, 11:21 AM

I think I figured it out. I need to use the specific net names (such as PCIE) not the DIFF100 net when doing lenth matching.

However, the issue I have now is how do I length match a Tx and Rx when the Tx has capacitors inline meaning there are 2 nets to the TX and one to the RX? It tries to match both sides of the TX and the RX to the same length, so TX ends up twice as long.

angelsix , 10-21-2015, 12:56 PM

Sorted. I created an xSignal using the xSignal wizard, and specified the start and point point of each trace. The xSignal is very buggy but after messing around a little I got it working.

robertferanec , 10-22-2015, 12:58 AM

@angelsix you are maybe too quick and too eager to finish your PCB. You still may need to learn some things before you start doing layout for boards with high speed interfaces. I strongly recommend you to study some recommendations about high speed design routing before you continue. I really want to help you.

There are a few things in your screenshot what I would never do - e.g. I would not use 90 degree corners on high speed signals and I would not route PCIE signal between pads of capacitor. Also, from your question I can see, that you may be missing some information about the purpose of Differential pair routing - why we do it and how it should be done properly. Maybe this video can help you a little bit: High Speed PCB Design Rules (Lesson 4 of Advanced PCB Layout)

angelsix , 10-22-2015, 01:35 AM

Thanks. Video watched. New design...

robertferanec , 10-22-2015, 01:38 AM

Please watch the video. I am REALLY trying to help you.

angelsix , 10-22-2015, 02:22 AM

I've read the guidelines of many documents and followed them (track width, gaps, dont cross voids, symmetrical vias and traces as much as possible, line matching, no sharp bends, 3x width of trace on top of serp, 1.5x on any 45 degree angle and so on).

I'll re-watch your 4th video.

In the meantime here is the only improvement I could see to keep tracks same width for longer. Other than that right now I cannot see any issue.

robertferanec , 10-23-2015, 12:07 AM

It is better. This is one of the main reasons why it is so difficult to do design reviews. Even in this case I would probably routed it differently - I would play with it and tried to find the optimum way to keep the uncoupled length at minimum. Also, PCIE is not so strict for lengthmatching between TX and RX (I would probably try to route it similar length, but I would not do "waves" if it's not necessary). E.g. see this from COM Express Carrier Design Guide: Length matching between RX and TX pairs (inter-pair): No strict electrical requirements. Keep difference within a 3.0 inch delta to minimize latency