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QDrives , 12-17-2024, 11:59 PM

I assume two separate LDO's, one for analog and one for digital?
https://www.youtube.com/watch?v=A9Kvst8hl0M

Atta Rehman , 12-18-2024, 10:11 AM

for digital +3.3V

Atta Rehman , 12-18-2024, 10:12 AM

for analog +/- 2.5V

QDrives , 12-18-2024, 03:44 PM

Do you get your values at 20Hz?
If so, 20 [M?] / 2.048 [MHz] = 9.765625

If you make your picture any smaller, you might as well not post them at all.
I see inductors and ferrite beads on the outputs. Remove them.
https://www.youtube.com/watch?v=HaLMjVkKYMw
https://www.youtube.com/watch?v=U5_61EJlytc

Atta Rehman , 12-18-2024, 04:33 PM

YES , power spectral density Values starts near 20HZ () ,

Atta Rehman , 12-18-2024, 04:34 PM

and repeats harmonics 9.76HZ multiples.

Atta Rehman , 12-18-2024, 04:35 PM

YES , i already removed FB with 0603 ohm jumper 0R resistor . .

Atta Rehman , 12-18-2024, 04:41 PM

" Do you get your values at 20Hz?
If so, 20 [M?] / 2.048 [MHz] = 9.765625 "

yes _ exactly starts from 20HZ and multiples of 9.76HZ .

Atta Rehman , 12-18-2024, 04:42 PM

why it starts from 20Hz. and get harmonics of 9.76Hz , as frequency is 2.048 MHz

QDrives , 12-18-2024, 05:05 PM

The 'frequency' you **see** starts at 40 / 2.048 [MHz] = 19.53125.
What settings do you have set for the SINC filter?
What sample rate (output SINC filter) are you using?

Atta Rehman , 12-18-2024, 07:42 PM

1. Respectfully , X axis is HZ , First Peak starts at 19.53 HZ than 9.76 multiples peaks. it should be in MHZ harmonics peaks are in HZ. Don't under stand _40 digit._
2. ADS1299 has fix **third order SINC** filter **. (not programmable ).
3. i am using **250 SPS** data rate .

Atta Rehman , 12-18-2024, 07:53 PM

ADS _SPI CLK _10MHZ

QDrives , 12-18-2024, 10:19 PM

https://www.youtube.com/watch?v=mCWC0X2naY0
And yes, I know your X axis is in Hz.

Atta Rehman , 12-19-2024, 11:42 PM

thanks dear , I will share data after iteration and debugging update .

Atta Rehman , 02-08-2025, 12:02 PM

Hi @QDrives ,
respected Sir , hope you are fine .
let me share with you some findings about mentioned noise harmonics in PSD.

Atta Rehman , 02-08-2025, 12:02 PM

Hi ,Sir !@ QDrive
Previously we discussed,
 That, I made ESP32 board interfaced with ADC, data acquisition on Wi-Fi through ESP32.
 During data acquisition, I have experience noise peaks in 9.76 Hz frequency harmonics.
Power spectral density (PSD) of data shown in figure.

 During debug , I observe 9.76Hz glitch in power +3.3V , Oscilloscope picture shown in figure

 I made different iterations in firmware to get rout cause of this noise.
 I found that, when I decrease WIFI signal strength from 19dB to 13dB. (as shown in figure below)

 Noise intensity reduced little, Wi-Fi signal intensity have direct relation with noise in board power supply.
 Total board is operating on battery 3.7V with LDO( TLV75733) , and board current consumption 150mA .

PCB BOARD is 6 LAYER. (each layer as shown in figure )

Atta Rehman , 02-08-2025, 12:04 PM

Atta Rehman , 02-08-2025, 12:08 PM

Sir,
1. Please suggest how I can resolve this issue of power noise link with Wi-Fi signal strength.
2. Please suggest , What is route cause of this issue EMC/ EMI etc ?

Atta Rehman , 02-08-2025, 12:10 PM

@Robert Feranec , @QDrives please review this PDF document which has picture to explain . thanks

QDrives , 02-08-2025, 10:30 PM

If your 3.3V dips like that, it will screw up your measurements.
You need to split the power supply in a digital and analog supply.
Have large capacitance and filter on the common part.

Atta Rehman , 02-09-2025, 12:29 AM

Thanks , please share some link or diagram , how to add filter on common part ,
2. Where to place large capacitor , (either on analog LDO output ?)

Atta Rehman , 02-09-2025, 12:29 AM

Let me share with you power supply

QDrives , 02-09-2025, 12:33 AM

Atta Rehman , 02-09-2025, 02:35 PM

sir , this power scheme was implemented.

Atta Rehman , 02-09-2025, 02:35 PM

Atta Rehman , 02-09-2025, 03:16 PM

5v source is 3.7 volt battery 🔋

QDrives , 02-09-2025, 08:59 PM

Is that 2.5V also supplying the VddA?
How big capacitance do you have on the 3.3V? And what kind of capacitors?
What filtering did you put in front of the LDO to the +2.5V and -2.5V?
What is the PSRR of the (analog) LDO's

Atta Rehman , 02-09-2025, 09:23 PM

Q: Is that 2.5V also supplying the VddA?
A : yes this 2.5V for ADC VDDA .
Q:/ capacitor size at 3.3 V LDO .
A:/ 10 µF ±10% 4V Ceramic Capacitor X6S 0603
Q:/ what filtering at LDO of , +2.5V , -2.5V.
A:/ LC filter at output of Analog LDO , C 2.2uF , L_3.3uH , C_10uF

Q:/PSRR of Analog VDDA.
A:/ TLV70025 , for 2.5V , 68dB as shown in figure

Atta Rehman , 02-09-2025, 09:50 PM

PSRR of LDO's are
1. for 3.3V , TLV75733PDBVR, 45dB figure 3:
2. for +2.5v , TLV70025DDCT , 68 dB figure 1:
3. for -2.5v ,TPS72325QDBVRQ1 , 65 dB figure 2:

QDrives , 02-09-2025, 10:45 PM

What is the rise and fall time of the dip in 3.3V?

Atta Rehman , 02-11-2025, 02:54 AM

+3.3V has " 1.93mSec" low time .
* Rise and fall time 0.3mSec (300usec approx)

Atta Rehman , 02-11-2025, 02:56 AM

i monitor analog voltage of ADC as well .
> +2.5V (analog ) , which is smooth
> -2.5V has voltage dip same as 3.3V .

Atta Rehman , 02-11-2025, 02:59 AM

QDrives , 02-11-2025, 03:28 AM

Are you sure that you really have the TLV75733 on your board?
The 3.3V in your pdf has a RMS value of 2.87V. Dip Vpp is 487mV. Too low and too much.
Better also make some measurements of the -3.3V and, more importantly, the +5V.

Atta Rehman , 02-12-2025, 12:30 AM

Q./ Are you sure that you really have the TLV75733 on your board?
A./ yes , Sure . (I sold it by self ).
*. I track back voltage dip source . Battery voltage probed also has voltage dip . (when wifi power at 19dBm). i.e . Does it means battery does not able to provide instant current spike . (battery connected is Li-ion_3.7V_14500 size _850mAH).

Atta Rehman , 02-12-2025, 12:33 AM

Battery voltage became stable , when I OFF Wi-Fi on board .

Atta Rehman , 02-12-2025, 12:46 AM

Sir , Battery voltage became stable and smooth . when i OFF Wi-Fi .
which capacitor will be better to connect across battery terminal ? (ceramic non polar / polar ).

QDrives , 02-12-2025, 01:05 AM

Your "3.3V" is already below 3.3V so the LDO does not do anything.
In fact, the drop out voltage is 475mV, so if you have 3.7V on the battery, the LDO has nothing to regulate.

QDrives , 02-12-2025, 01:06 AM

Second problem is that the 3.3V seems stable low. So your battery and circuit to the 3.3V has lots of losses.

QDrives , 02-12-2025, 01:07 AM

You either need a buck-boost circuit to keep 3.3V or lower loss circuit, especially the "LDO".

Atta Rehman , 02-12-2025, 01:09 AM

Normally battery full charge
Starts at 4.2V and I defined 3.6V auto shutdown in circuit .

QDrives , 02-12-2025, 01:11 AM

So what is the voltage:
a) Across the battery
b) before the LDO
c) After the LDO

Atta Rehman , 02-12-2025, 01:11 AM

This is battery 🔋 probing picture 4.05 V.

QDrives , 02-12-2025, 01:12 AM

And again, if you set it to 3.6V, you cannot use a LDO with 475mV dropout. You need one with something like 200mV.

QDrives , 02-12-2025, 01:13 AM

Did you try another battery?

Atta Rehman , 02-12-2025, 01:14 AM

When I connect , PC _USB cable along with battery also with board , voltage dip minimized .

QDrives , 02-12-2025, 01:14 AM

So the battery is not able to keep a constant voltage when loaded.

QDrives , 02-12-2025, 01:15 AM

What is voltage (b) do between the charger IC and the LDO?

Atta Rehman , 02-12-2025, 01:17 AM

Seems like .
*Also there is stable positive 2.5v.
* Dip only observe in negative 2.5V.
* Voltage at battery now 4.01 volt at LDO input 3.89 V and LDO output 3.31 with DMM.

QDrives , 02-12-2025, 01:38 AM

So the resistance in your charger IC is too big.