FEDEVEL
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zubianiko , 04-03-2019, 01:41 AM

Hello Robert,
My componetsare covered and full with net names. only the power lines that are not. How do I correct these? Below is how it looks like

Paul van Avesaath , 04-03-2019, 02:08 PM

looks to me like your schematic symbol is not correct.

robertferanec , 04-08-2019, 01:19 AM

I am not sure what the problem is - do you mean, you can not see net names on some of the pads? You may need to zoom in closer.

zubianiko , 04-11-2019, 08:52 PM

This is the errors and I have tried for some days to fix them. They are 87 of them. Is there any idea how I can finish this project because this is what is holding me back. Hello Robert i sent you an email of this project. The video clips seems not to tell us how to fix problems like these.

robertferanec , 04-12-2019, 01:21 AM

Did you assign net to GND planes? You need to go on L2 and L5, double click on the plane and assign it to GND.

This may help (minute 4:05): https://www.fedevel.com/welldoneblog...e-new-old-way/

zubianiko , 04-17-2019, 10:47 AM

Hello Robert I did as you said and the error wnent down from 87 to only 9 errors remaining. This error says so Hole Size Constraint: (1.5mm > 1mm) Pad J1-1(60.696mm,29.757mm) on Multi-Layer Actual Hole Size = 1.5mm . How do i fix it or is is a problem at all. Another thing also I don't know what layer you made 5V PVCC to have. My 5V PVCC is without a layer.

robertferanec , 04-24-2019, 06:10 AM

Maybe it is the hole size rule what you need to correct? You can download the finished project from the course page and double check my settings and layout. +5V_PVCC is just a track on bottom layer.

Paul van Avesaath , 04-24-2019, 06:54 AM

looking at your pdf and see only net antenna errors..

net antenna is usaully a piece of track (or a dot) on your via.. try and remove it... sometimes this happens, but since you specified 0mil tolerance

go to singel layer mode go to L1 or L6 and see if you can select everything underneath the via..