Fanout Via Placement - Lesson 3 of Advanced PCB Layout Course
Tom Yunghans , 04-28-2020, 10:57 PM
Hi Robert,
In performing the fanout of the BGA, I found that it was sometimes useful to move vias slightly to make room for the other vias or tracks. The fanout vias for a particular pad all are assigned the same net, so I am questioning just how close they can be to each other. Can you comment on the four cases I created below?
Cases #1 and #2 can be used for fanout of the BGA on L3; cases #3 and #4 could be used for fanout of the BGA on L10.
Case #1 is used in your original design of the module quite frequently and has a 0.154mm clearance between pads on L2, which is greater than 0.1mm, so no issue. Is case #2 an issue? In that case there is only a 0.013mm gap between the pads. This is not a problem electrically, as they are both assigned the same net, but would the PWB manufacturer have a problem with that?
In case #3, the gap between pads on L3 is only 0.04mm (which is considerably less than 0.1mm). You used this configuration quite often in your design, so I assume it must not be an issue. How about case #4? In that case the pads on L3 are actually overlapping. Is this considered a "stacked via" and should be avoided?
Thanks!
In performing the fanout of the BGA, I found that it was sometimes useful to move vias slightly to make room for the other vias or tracks. The fanout vias for a particular pad all are assigned the same net, so I am questioning just how close they can be to each other. Can you comment on the four cases I created below?
Cases #1 and #2 can be used for fanout of the BGA on L3; cases #3 and #4 could be used for fanout of the BGA on L10.
Case #1 is used in your original design of the module quite frequently and has a 0.154mm clearance between pads on L2, which is greater than 0.1mm, so no issue. Is case #2 an issue? In that case there is only a 0.013mm gap between the pads. This is not a problem electrically, as they are both assigned the same net, but would the PWB manufacturer have a problem with that?
In case #3, the gap between pads on L3 is only 0.04mm (which is considerably less than 0.1mm). You used this configuration quite often in your design, so I assume it must not be an issue. How about case #4? In that case the pads on L3 are actually overlapping. Is this considered a "stacked via" and should be avoided?
Thanks!
robertferanec , 04-30-2020, 08:57 AM
Standard rule for hole to hole clearance is 0.2mm (but double check with your PCB manufacturer). I think, laser drilled VIAs can be closer (0.1mm???) but I would not go so close.
Generally I do no place VIAs the way that they would be touching (I keep some space between them).
If possible, I try to place them the way that the smallest distance between them is no smaller than minimum clearance (so the small space between them is manufactured without any problems). But sometimes I can go closer.
Generally I do no place VIAs the way that they would be touching (I keep some space between them).
If possible, I try to place them the way that the smallest distance between them is no smaller than minimum clearance (so the small space between them is manufactured without any problems). But sometimes I can go closer.
Tom Yunghans , 04-30-2020, 09:30 AM
Thanks for responding. Do you ever try to set a rule to warn you if you get too close? The existing general "clearance" rule is set to "Different Nets Only", so I assume that is why it doesn't flag this as a violation. Just changing that parameter to "All Nets" gives you a lot of violations you don't want (e.g. like dropping a via in the middle of a polygon pour). Perhaps playing with the table in the "clearance" rule can get you what you want?
robertferanec , 05-04-2020, 03:24 AM
No, I do not usually set that rule - just visually and if I need I can measure it.
PS: But if you need you can set also rules for objects on the same net or any net (and you can adjust clearance between objects in the matrix e.g. VIA to VIA)
PS: But if you need you can set also rules for objects on the same net or any net (and you can adjust clearance between objects in the matrix e.g. VIA to VIA)
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