DDR3 2 Layer routing
suleymancskn , 08-17-2020, 05:15 AM
Hi Robert,
I have already completed a 6 layer 32 bit dual ddr3 design. Our design works well.
But now I am asked to design 16 bit ddr3 with 2 layers.
Theoretically, I think there will be problems with impedance and cross talk.
I am curious about your opinion on the subject.
Thank you.
I have already completed a 6 layer 32 bit dual ddr3 design. Our design works well.
But now I am asked to design 16 bit ddr3 with 2 layers.
Theoretically, I think there will be problems with impedance and cross talk.
I am curious about your opinion on the subject.
Thank you.
suleymancskn , 08-22-2020, 03:03 AM
Hello, I'm curious about your thoughts on the subject.
@robertferanec
@Lakshmi
@robertferanec
@Lakshmi
Lakshmi , 08-22-2020, 05:05 AM
Hi,
I have no experience in DDR routing. Maybe @@robertferanec or @@Paul van Avesaath could give suggestions.
The minimum stack-up with DDR, I've seen so far is 4 Layer.
Yes, You might have to worry about SI Problems as in 2 Layers you can not achieve a continuous ref plane in 2 layers. you need to do the SI and PI simulations.
I'd suggest you switch to 4 Layers rather than 2
I have no experience in DDR routing. Maybe @@robertferanec or @@Paul van Avesaath could give suggestions.
The minimum stack-up with DDR, I've seen so far is 4 Layer.
Yes, You might have to worry about SI Problems as in 2 Layers you can not achieve a continuous ref plane in 2 layers. you need to do the SI and PI simulations.
I'd suggest you switch to 4 Layers rather than 2
suleymancskn , 08-22-2020, 06:42 AM
Hi,
I have no experience in DDR routing. Maybe @@robertferanec or @@Paul van Avesaath could give suggestions.
The minimum stack-up with DDR, I've seen so far is 4 Layer.
Yes, You might have to worry about SI Problems as in 2 Layers you can not achieve a continuous ref plane in 2 layers. you need to do the SI and PI simulations.
I'd suggest you switch to 4 Layers rather than 2
I have no experience in DDR routing. Maybe @@robertferanec or @@Paul van Avesaath could give suggestions.
The minimum stack-up with DDR, I've seen so far is 4 Layer.
Yes, You might have to worry about SI Problems as in 2 Layers you can not achieve a continuous ref plane in 2 layers. you need to do the SI and PI simulations.
I'd suggest you switch to 4 Layers rather than 2
Thank you @Lakshmi
I think it has 4 layers too. But I'm trying to prove it.
I think the data will be lost due to cross talk as PP thickness increases and there is no reference plane.
robertferanec , 08-24-2020, 07:56 AM
But now I am asked to design 16 bit ddr3 with 2 layers.
suleymancskn , 08-24-2020, 08:11 AM
Hello, I have one 16 bit DDR3. Clock frequency is 360MHz.
Remember the name of the 2L card, which is the only DDR3 card you've seen before? Was it open source?
Also, since the processor is a QFP chassis, the length matching process is quite challenging. Do you have any suggestions on this matter?
Thank you so much...
robertferanec , 08-25-2020, 01:16 AM
I have searched for the board what I have seen with DDR3 on 2 Layers, but I can't remember which one it was. I believe it was a reference board from a well known chip manufacturer or an open source board, but I really do not remember what board it was 
Still maybe 1 chip placed close could run at 360MHz on 2 layer. Personally, I would not do it (I would use at least 4 layers), but if you are creating a very cost sensitive board, it may be possible to do it after careful and extensive testing (possibly some simulations),
Still maybe 1 chip placed close could run at 360MHz on 2 layer. Personally, I would not do it (I would use at least 4 layers), but if you are creating a very cost sensitive board, it may be possible to do it after careful and extensive testing (possibly some simulations),
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