BGA 800 PAD 0.4 mm pitch
hajri_abderaouf , 03-01-2016, 01:56 AM
the attached picture is the footprint and the lib of the bga..my client ask me if i can root this CPU on 6 layer pcb using only through hole vias,is that possible? i had choose to use vias with 0.1 hole and 0.25 diameter,but i'm not yet able to fix the width and clearence.can some one help me with those dimension? what value should i set in solder mask expansion.
robertferanec , 03-01-2016, 02:12 AM
@hajri_abderaouf 
If I was you, I would talk to your PCB manufacturer and ask them what is the smallest through hole VIA they can manufacture. You may be surprised how big the smallest through hole VIA will be.
Have a look at the reference design of the CPU. That will give you an idea of how to route it, what VIAs to use and how complex it will be.
If I was you, I would talk to your PCB manufacturer and ask them what is the smallest through hole VIA they can manufacture. You may be surprised how big the smallest through hole VIA will be.Have a look at the reference design of the CPU. That will give you an idea of how to route it, what VIAs to use and how complex it will be.
hajri_abderaouf , 03-01-2016, 03:52 AM
it's a freelance job,so i have no idea about where to manufacture the board,i had search the net for many hour i haven't find any design guide,the cpu is SC54412..
mairomaster , 03-01-2016, 09:35 AM
Hi hajri_abderaouf,
Google tells me that is a Samsung Exynos CPU. Currently I am working on a design using Samsung Exynos (although it is a different series with 0.5 mm pitch) and from experience I can tell you that probably you will not be able to find much documentation on the web. Samsung requires NDA for all kinds of documents regarding those. I advice you to ask your client to prepare and NDA so he can give you some documents provided to him by Samsung, or if he doesn't have any he can request some. That is all provided that he has support from Samsung, if he doesn't have support he should be quite crazy in my opinion, to start a design with such CPU.
In the design I work on we are using 0.1 mm hole 0.25 mm pad micro vias in pad, to fan out the processors and it is working well. In your case things are even more difficult since the pitch is 0.4 mm. I can't see how this could work with TH vias, considering how big the chip is. Another thing is that you might struggle laying it out on 6 layers only, depending on how many signals you have.
This video provides some useful information about the difficulties with fanning out small pitch BGAs, although it uses as an example a much smaller package:
Google tells me that is a Samsung Exynos CPU. Currently I am working on a design using Samsung Exynos (although it is a different series with 0.5 mm pitch) and from experience I can tell you that probably you will not be able to find much documentation on the web. Samsung requires NDA for all kinds of documents regarding those. I advice you to ask your client to prepare and NDA so he can give you some documents provided to him by Samsung, or if he doesn't have any he can request some. That is all provided that he has support from Samsung, if he doesn't have support he should be quite crazy in my opinion, to start a design with such CPU.
In the design I work on we are using 0.1 mm hole 0.25 mm pad micro vias in pad, to fan out the processors and it is working well. In your case things are even more difficult since the pitch is 0.4 mm. I can't see how this could work with TH vias, considering how big the chip is. Another thing is that you might struggle laying it out on 6 layers only, depending on how many signals you have.
This video provides some useful information about the difficulties with fanning out small pitch BGAs, although it uses as an example a much smaller package:
robertferanec , 03-01-2016, 10:02 AM
The BGA pitch is very small. You should be talking to a PCB manufacturer or at least to know what other people used to fan the BGA out. I am sure you don't want to finish the layout and find out that no one can manufacture the PCB you designed. Just to give you an example, here you can find some info about PCBs what we normally use: http://www.fedevel.com/welldoneblog/...clearance-via/
You may notice, that through hole VIAs which we use are 0.45/0.2mm and uVIAs are 0.25/0.1 (very often we actually use 0.27/0.1mm).
So, what I am saying is the same as @mairomaster explained - you may need to use uVIAs to fanout the CPU.
You may notice, that through hole VIAs which we use are 0.45/0.2mm and uVIAs are 0.25/0.1 (very often we actually use 0.27/0.1mm).
So, what I am saying is the same as @mairomaster explained - you may need to use uVIAs to fanout the CPU.
hajri_abderaouf , 03-01-2016, 10:02 AM
Thanks mairo for your response
i start to fanout this CPU,i found that there is a chance to root it in 6 layer,but only if i use clearence < 0.1,in my whole life i had use 0.1 as the minimun clearence so i don't know if 0.05 does really exsit or no.i also find vias with 0.1 hole 0.2 diameter very useful.
i start to fanout this CPU,i found that there is a chance to root it in 6 layer,but only if i use clearence < 0.1,in my whole life i had use 0.1 as the minimun clearence so i don't know if 0.05 does really exsit or no.i also find vias with 0.1 hole 0.2 diameter very useful.
robertferanec , 03-01-2016, 10:07 AM
The smallest track/clearance I have ever used are 0.075/0.075mm .... it looks to me like this is a limit for most of the PCB manufacturers. I have seen even smaller tracks, but I am not sure what they can guarantee then and how many PCB will be wasted due PCB manufacturing problems.
mairomaster , 03-02-2016, 06:25 AM
This is the manufacturer we normally use at our company:
Different things need to be considering when working with such small clearances:
- Copper to copper clearance - probably the most obvious one. The value might need to be more on plated layers (top and bottom for example, but could be some others as well), since because of the plating they cannot achieve such a good accuracy. The values for plated and non-plated layers are normally given by the PCB manufacturer. It also depends which technology you want to use, for better technologies you are getting better values, but you pay more. With Stevenage we can get down to 50 um for none-plated layers and 76 um for plated layers using the most advanced technology.
- Track thickness - again it goes down to 50/76 um with the best technology offered by Stevenage.
- Minimum mechanical hole - concerns TH vias. Goes down to 0.15 mm. It is very important to know that this is the size of the drill piece they use to drill the holes. If in Altium you have 0.2 mm via hole for example, that is the finished hole diameter after plating. Because of the plating thickness, they always need to use a bigger drill size, so there is enough space for the plating and after the plating you will get a finished hole diameter of 0.2 mm as desired. With one of my boards they needed to use 0.3 mm drills for the 0.2 mm via holes. We were fortunate that this was not a problem with the particular board, but it could be in many cases. So always keep that in mind when you set up rules and work out clearances.
- Minimum laser hole - concerns micro vias. Goes down to 60 um. The aspect ratio (depth to diameter) is quite small with micro vias (as Robert explains well in the Advanced Layout course) and that should be always considered. With Stevenage it can be up to 1.3:1. That means that if you have a micro via with a hole diameter of 0.1 mm it can go a maximum of 0.13 mm in depth. That will normally be just the distance between two layers next to each other. If you decide to go with a very small micro vias (0.06 mm lets say) you might found that they can't be long enough to connect two layers in your stack.
- Minimum micro via pad - goes down to 188 um for the surface layer (top/bottom) and 138 um for inner layers. Using vias in pads helps to gain additional space as well, to do some routing on the top layer, but requires a more advanced technology and might lead sometimes to problems with successful soldering of the BGA.
- Minimum solder mask expansion/Minimum solder mask sliver. If you use too small of a value for the expansion, you risk some pads to be partially covered by solder mask after manufacturing. If you use too small of a value for the solder mask sliver, you risk getting shorts between pads. To prevent such problems, I found it is a good practice for example to cover (tent) vias which are underneath a BGA. With Stevenage the minimum expansion you can have is 25 um and the minimum sliver is 76 um.
Again all of that should be checked with the particular manufacturer prior to starting the design, since as Robert explained you might easily find that they either can't manufacturer the board or the yield could be pretty low.
Different things need to be considering when working with such small clearances:
- Copper to copper clearance - probably the most obvious one. The value might need to be more on plated layers (top and bottom for example, but could be some others as well), since because of the plating they cannot achieve such a good accuracy. The values for plated and non-plated layers are normally given by the PCB manufacturer. It also depends which technology you want to use, for better technologies you are getting better values, but you pay more. With Stevenage we can get down to 50 um for none-plated layers and 76 um for plated layers using the most advanced technology.
- Track thickness - again it goes down to 50/76 um with the best technology offered by Stevenage.
- Minimum mechanical hole - concerns TH vias. Goes down to 0.15 mm. It is very important to know that this is the size of the drill piece they use to drill the holes. If in Altium you have 0.2 mm via hole for example, that is the finished hole diameter after plating. Because of the plating thickness, they always need to use a bigger drill size, so there is enough space for the plating and after the plating you will get a finished hole diameter of 0.2 mm as desired. With one of my boards they needed to use 0.3 mm drills for the 0.2 mm via holes. We were fortunate that this was not a problem with the particular board, but it could be in many cases. So always keep that in mind when you set up rules and work out clearances.
- Minimum laser hole - concerns micro vias. Goes down to 60 um. The aspect ratio (depth to diameter) is quite small with micro vias (as Robert explains well in the Advanced Layout course) and that should be always considered. With Stevenage it can be up to 1.3:1. That means that if you have a micro via with a hole diameter of 0.1 mm it can go a maximum of 0.13 mm in depth. That will normally be just the distance between two layers next to each other. If you decide to go with a very small micro vias (0.06 mm lets say) you might found that they can't be long enough to connect two layers in your stack.
- Minimum micro via pad - goes down to 188 um for the surface layer (top/bottom) and 138 um for inner layers. Using vias in pads helps to gain additional space as well, to do some routing on the top layer, but requires a more advanced technology and might lead sometimes to problems with successful soldering of the BGA.
- Minimum solder mask expansion/Minimum solder mask sliver. If you use too small of a value for the expansion, you risk some pads to be partially covered by solder mask after manufacturing. If you use too small of a value for the solder mask sliver, you risk getting shorts between pads. To prevent such problems, I found it is a good practice for example to cover (tent) vias which are underneath a BGA. With Stevenage the minimum expansion you can have is 25 um and the minimum sliver is 76 um.
Again all of that should be checked with the particular manufacturer prior to starting the design, since as Robert explained you might easily find that they either can't manufacturer the board or the yield could be pretty low.
robertferanec , 03-02-2016, 08:45 AM
@mairomaster If I could, I would give you more likes for the post above Excellent explanation! I didn't know about the 50/75um track width, very good info.
Excellent explanation! I didn't know about the 50/75um track width, very good info.hajri_abderaouf , 03-02-2016, 10:02 AM
Thanks mairomaster for this explanation..those information are important to know
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