question about signal inner layer of PCB
BorisXXX , 09-26-2016, 01:13 PM
Hello everyone,
I try to describe my tricky situation. I am making 6th layer PCB in altium and I dont sure if I have to fill 3th and 4th layer by GND (whole layer or part of layer). 3th and 4th layer contains only buses from LPDDR, FLASH, uSD, I2C, I2S, USB, SPI. I will be very glad for every tips.
I attach some pictures of my PCB below
I try to describe my tricky situation. I am making 6th layer PCB in altium and I dont sure if I have to fill 3th and 4th layer by GND (whole layer or part of layer). 3th and 4th layer contains only buses from LPDDR, FLASH, uSD, I2C, I2S, USB, SPI. I will be very glad for every tips.
I attach some pictures of my PCB below
BorisXXX , 09-26-2016, 01:15 PM
I attach still last layer BOTTOM
robertferanec , 09-26-2016, 02:08 PM
Following is my own personal opinion, it is what I tested on many boards an it always has worked. This doesn't mean, that other solutions (including yours) are good or bad.
- I always have at least one solid GND plane. Above / below this plane I route all the important signals (e.g. memory bus, differential pair signal).
- I try to avoid routing in parallel on neighbor layers
- it is very unusual to see this kind of nice fanout on our boards (the kind of fanout which is very nice pin-to-via connection). When we do fanout, often we use it to swap signals on top / bottom layer, so we can use inner layers more efficiently (on our PCBs we squeeze a lot of tracks on one layer).
In your case, I would do it like:
TOP (L1) - GND (L2) - Signals L3 (keep it closer to the GND, thinner dielectricum between GND-Signals than Signals-Power) - Powers (L4) - GND (L5) - BOTTOM. You only have through hole VIAs and fanout under the BGA will be really tough, but it could be possible. If not, I would change Powers (L4) to one biggest power you have on the board (e.g. 3V3) and I would maybe use L5 for local powers plus signals ... or something like this
- I always have at least one solid GND plane. Above / below this plane I route all the important signals (e.g. memory bus, differential pair signal).
- I try to avoid routing in parallel on neighbor layers
- it is very unusual to see this kind of nice fanout on our boards (the kind of fanout which is very nice pin-to-via connection). When we do fanout, often we use it to swap signals on top / bottom layer, so we can use inner layers more efficiently (on our PCBs we squeeze a lot of tracks on one layer).
In your case, I would do it like:
TOP (L1) - GND (L2) - Signals L3 (keep it closer to the GND, thinner dielectricum between GND-Signals than Signals-Power) - Powers (L4) - GND (L5) - BOTTOM. You only have through hole VIAs and fanout under the BGA will be really tough, but it could be possible. If not, I would change Powers (L4) to one biggest power you have on the board (e.g. 3V3) and I would maybe use L5 for local powers plus signals ... or something like this
BorisXXX , 09-27-2016, 05:32 AM
Thank you very much for your tips.
I was inspirated by this article when I thought about number of layers http://www.dps-az.cz/cad-cam-cae/id:...vicevrstve-dps
Whole L2 is solid and this layer is connected completely to GND and analog GND apart from small area which is related with antenna of bluetooth. L5 contains very voltage branchs and again whole solid. I know that two GND layer are better for EMC but 6th layer is compromise between price and complexity. This PCB has been school project. I will hope that there will be minimum crosstalk and other parasitive properties. I attach thickness every single layers ( picture from layer stack manager). PCB is almost completely and I am not sure if change of layer is suitable .
I have one short question:
I would like to know is suitable to add line of GND between buses in layer L3 and L4 or to fill these layer some area of GND.
Best regards
BorisXXX
I was inspirated by this article when I thought about number of layers http://www.dps-az.cz/cad-cam-cae/id:...vicevrstve-dps
Whole L2 is solid and this layer is connected completely to GND and analog GND apart from small area which is related with antenna of bluetooth. L5 contains very voltage branchs and again whole solid. I know that two GND layer are better for EMC but 6th layer is compromise between price and complexity. This PCB has been school project. I will hope that there will be minimum crosstalk and other parasitive properties. I attach thickness every single layers ( picture from layer stack manager). PCB is almost completely and I am not sure if change of layer is suitable .
I have one short question:
I would like to know is suitable to add line of GND between buses in layer L3 and L4 or to fill these layer some area of GND.
Best regards
BorisXXX
robertferanec , 09-27-2016, 08:38 AM
I would like to know is suitable to add line of GND between buses in layer L3 and L4 or to fill these layer some area of GND.
PS: Some time ago I read an article, that improperly poured copper between tracks can make the PCB worse - explanation was, that if this copper is not properly connected, some pieces of the poured copper can work like antennas.
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