This page details the Connection Matrix tab of the Project Options dialog, which provides a mechanism to establish connectivity rules between component pins and net identifiers, such as ports and sheet entries
This page details the Error Reporting tab of the Project Options dialog, which enables you to define the reporting levels for each of the possible electrical and drafting violations that can exist on source schematic documents when validating the project
You have to be careful would de-activating different options though - it might let some real problem through. Make sure that you understand each error and carefully check the schematics if it is a real problem or not. Another useful thing to do is to put "specific no error ERC" directives on particular nets that need to be excluded from the general check:
This page details the schematic No ERC object - a design directive placed on a node in the circuit to suppress all reported ERC validation warnings/errors. Covers availability and placement, as well as graphical and non-graphical editing
sneha.xeye , 02-02-2017, 09:26 PM
is it create problem in the PCB layout if multiple input or output ports are not a real problem & we ignore this kind of errors?
mairomaster , 02-03-2017, 01:59 AM
No, it will be fine with the layout. This particular error (and many others) is only to signal to you that it might be dangerous in some cases.
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