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popest , 09-07-2017, 07:38 AM

Hello,

I have a question about using blind VIAs which are contacting TOP and the second layer (reference plane) in combination with a high-speed design. My design is 8 layers PCB. TOP-GND1-sig1-PWR-GND2-Sig2-GND3-Bottom. I have a connector with BGA footprint (0.8mm). In sig1 and sig2 are high-speed differential pairs. The BGA footprint has a lot of pads which must be connected to the GND plane. For this connection, I combine classical THT VIA with blind VIA (drill pair TOP-GND1) due to creating some free space for diff. pairs in inner layers. If I am not wrong the place where blind VIA contacts GND plane will create a small circle with the same diameter as blind VIA drill where copper is missing.

Can this violation integrity of reference plane cause some impedance problem in diff. pairs in inner layer sig1?

Now, I am trying to move out all blind VIAs which were directly on the same position like diff. pair, because I think that it is better has it alongside diff. pair than inside diff. pair but it is not possible for all VIAs.

What is your opinion?

I am attaching a figure with screenshot form Altium.

Thank you very much.

robertferanec , 09-08-2017, 02:37 PM

Honestly, I have never used it like this. For powers and grounds I always use through hole VIAs (I have only made a very few exceptions). I prefer through hole as in most cases there are decoupling capacitors placed on the bottom. Also, through hole connects all the GND planes together which may be good if you use them as reference planes and also it helps to take heat awayf from the BGA component. I see you only used it in a few places, maybe that could be ok.

I believe, if you connect L1 to L2 through GND blind VIA where L2 is GND plane, there should not be a problem (there should not be a circle):

popest , 09-08-2017, 03:57 PM

Thank you Robert, for the useful picture with cross section view. In this case everything should be ok. I will verify my PCB manufacturer if their blind VIAs are done in the same way. I also use THT VIAs for power connection but this is just footprint for a connector (Samtec Z-ray) which is used for FPGA module connection (there should be no heat transfer). In the picture which I have posted are few blind VIAs but actually, I have changed practically all VIAS close to diff pairs to blind VIAS due to keeping L4 layer (PWR plane) consistent because it is used as the second reference plane for Sig1 and the high count of GND THT VIAs broke this layer. I hope that this approach is correct. What do you think?

I attach screenshot how it looks.

Thank you very much.

popest , 09-11-2017, 04:37 AM

Hello Robert,

Could you tell me please name of the manufacturer which is able to do blind VIAs like on your picture which you have posted here? I have contacted my PCB manufacturer and they are not able to do it like this. For reliable connection the second layer will be drilled too thus it will create a circle without copper.

Thank you very much.

robertferanec , 09-12-2017, 04:36 PM

The picture is from our Slovak PCB manufacturer: http://www.sqpinternational.com/ But I guess also other manufacturers should be able to do it.

PS: To answer your previous question, if I think if it is ok using uVIAs for GND ... I do not use uVIAs for GND, so I do not really know how it will influence power distribution.