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Via , 11-13-2017, 07:09 PM

Hi Robert,

I finished already the length matching under xSignal rules, I used 5.9 mil track width depend on your 6 layer stack up suggestion.
the Clearance between track is minimum 5 mil and in Diff are 30 mil ( Diff width is 6 mil).
I just worry about cross talk between then? what can I do more to improve the drawing.

Thanks in advance.

robertferanec , 11-14-2017, 09:17 AM

Hmm, I never use so small space inside the waves. If I can, I setup the space inside waves 5x Track width, or minimum 3x Track width.

Via , 11-14-2017, 11:03 AM

Yes, But there is no space for that I used rule as track distance 5 mil to generate the waves, is it not correct?

robertferanec , 11-14-2017, 11:29 AM

If your track width is 6mils, the minimum space between waves should be at least 18mils.

You have plenty of space, trust me

Via , 11-14-2017, 12:02 PM

OMG! I need to redraw all!
Yes , But I used the shortest way to connect them, There is no limitation on Track length in DDR3 connection? I think that I going over 5 cm!

Via , 11-14-2017, 12:25 PM

Thanks I thought the rules for waves clearance is the sames rules for track!
Can we define as wave clearance rule in Altium to check all of them?

Via , 11-14-2017, 12:45 PM

I see 2x wide in waves in my reference design board from Olimex, I opened the board in KiCad and use as references.
Do you have experience working wit KiCad?
I want to know to to get distance between two tracks?

Via , 11-14-2017, 06:50 PM

Updated! What do you think?

robertferanec , 11-15-2017, 08:47 AM

These waves are much better. BTW, what is this interface and topology? I am just curious.

Via , 11-15-2017, 10:39 AM

Yes,Sure. Its A64 Allwinner cpu with 1G DDR3 (K4B4G1646E-BYK0), as I told you I used Olimex A64 board (open hardware) as reference.
the topology is Fly-by.

Via , 11-15-2017, 04:16 PM

Robert do you accept this routing for 1G ethernet? or UDRD0_P is very close to UDRD1_N? distance is less more than 6mil.

robertferanec , 11-17-2017, 04:31 PM

I often use minimum clearance between track-and-VIA or track-and-pad (even when I route differential pairs, they are often routed very close to VIAs or pads) - so this should be ok. Also, when routing differential pairs close to each other, I always try to keep distance between differential pairs bigger than distance between + & - signals, but as big as I can - that looks also ok.

However, what you may want to correct is same_net-same_net clearance. For example have a look at UDRTR3_P - seems to me routed too close to the UDRTR3_P pin. You will not get an error as it it the same net, however, the space between the track and pad may be too small to be manufactured.

Via , 11-20-2017, 10:36 AM

Thank you for feedback, Yes I corrected them depend on your suggestion.
My pcb is ready for manufacturing and I finalizing the board.
I have two question:
I have some dead polygon between my DDR3 tracks, is good to ground them with via?
and also I make length-matching in all diff pair but Altium detect them as gab differences from my defined rules for differential routing rules, I defined a room for places in area ( by example close to HDMI component to ignore them, but doesn't work!
Interesting that I made DRC check on OpenRex board and get same error!!

, 11-21-2017, 08:04 AM

In case of using the waves to match the length of tracks, how can we guarantee that space between two adjacent track is x3 times of width of track (for preventing crosstalk).

, 11-21-2017, 08:09 AM

From EMC point of view, no polygan is better than floating ploygan, becuase it increases the coupling capacitance and they cause crosstalk. So, connect them to GND by via or remove it

robertferanec , 11-21-2017, 12:56 PM

Altium is not good in fitting the waves into small space. So very often I do the waves manually e.g. I create one and then copy and paste it ... or I just draw it. When you draw the waves, you will get the idea what the space between the tracks should look like (you can also measure it). If you use interactive length tuning, then set "Gap" to be 3x track width (often I route 50OHMs by 0.1mm, so I use space 0.3mm)

robertferanec , 11-21-2017, 01:01 PM

Can you attach screenshots?

zagrosmega , 11-22-2017, 05:20 AM

so i think that in OpenRex pcb(imx6) many signal traces like ddr3 data line and address line are routed with this method ok?and does it means that (length matching rules) in altium designer cannot be useful in some cases ,because altium uses standard wave shape for length tuning .

robertferanec , 11-22-2017, 05:39 PM

- yes, waves in OpenRex are done manually
- wave shape doesn't influence length matching and it is still useful to setup the rules. Maybe this can help: https://www.fedevel.com/welldoneblog...useful-things/

Via , 11-26-2017, 02:57 PM

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Via , 11-26-2017, 02:58 PM

Sorry for delay , here is errors from your projects

robertferanec , 11-27-2017, 10:45 AM

This is uncoupled length. We set it intentionally low, so Altium then highlights all the segments which have the uncoupled length (the places where space between tracks is different as specified by stackup and impedance). It is not length matching.

Via , 11-27-2017, 01:42 PM

Yes I know, How we can setup a rules for them? I had idea to define the room in area that we make space for length matching in Diff but doesn't work!

robertferanec , 11-27-2017, 06:08 PM

Please could you be more specific? I am not sure what rules you would like to set for what.
PS: You can always have a look at our open source designs to check how we set them up: http://www.imx6rex.com/

Via , 11-29-2017, 03:33 PM

The area like this. I need update the the max gap in Diff rules or there is another way to solve this problem?

robertferanec , 12-01-2017, 12:12 PM

This is called uncoupled length. You can set higher tolerance for it. Go to Design -> Rules -> Routing -> Differential pair routing: select your differential pair rule: set "Max Uncoupled Length" to higher number (you can check the longest uncoupled length in DRC report, so set it to be a little bit longer ... just be sure you are ok with all the uncoupled length). See the screenshot below: