FEDEVEL
Platform forum

Mshakeri65 , 01-11-2018, 05:32 PM

Hi,
I have two questions about DDRx VREF:

1.
Why do the DDRx VREF route with traces and not a plane or polygon? I see this method in IMX6 project and some other projects. Is there any consideration or limitation for using plane area for DDRx VREF?

2.
Where to place VREF resistor voltage divider (as VREF source) when we have 4 or more DDRx that connected to FPGA and so they are in different sides of FPGA? Should place VREF source near power section or ...? Is there any consideration?

Thanks

robertferanec , 01-11-2018, 07:10 PM

1) I use traces as I would like to have control how the currents of VREF are going to flow and I would like to keep it small as I do not want to pick it up noise.
2) I have seen the resistors placed in number of different places (middle, processor, end). Very often I place it the way so I can make a star connection to the individual memory chips and CPU. If you have more memory interfaces and CPU has VREF for each of them, you may be able to use more resistor dividers (check with reference schematic).

mohsin_qau , 01-14-2018, 10:38 PM

I have seen tutorial in NXP for DDR II and DDR III. in which they have given example of Vref/VTT with copper islands.

robertferanec , 01-15-2018, 01:38 PM

@mohsin_qau nice example. thanks for sharing