SDR SDRAM layout recommendations
faluco , 09-03-2015, 07:21 AM
Hello everybody,
I'm currently doing the layout of a board that has an STM32F4 microcontroller connected to a SDR SDRAM chip at 90MHz and a NOR flash chip (30MHz), both SHARING the same interface of the mcu (address + data).
I've been looking for layout recomendations, but only found some papers from Intel, focused on motherboards with RAM slots, or datasheets from other manufacturers with very vague information. I'm sort of worried about length matching, topology and line termination, specially for the bidirectional data bus termination. Does anybody have any hints or experience with these kind of interfaces?
Some more information:
The fastest edges are produced by the RAM chip (0.8ns) so they could produce some ringing, not worried about the microcontroller or the flash outputs. At the moment, I've placed series termination resistors in all lines (address + data + control lines) and since the data bus is bidirectional and the fastest edges come from the RAM chip, I'm placing those termination resistors near that output, rest of resistors are near the microcontroller outputs. I'm using the Y topology, keeping the branch lengths as short as possible.
Thanks for the help!
I'm currently doing the layout of a board that has an STM32F4 microcontroller connected to a SDR SDRAM chip at 90MHz and a NOR flash chip (30MHz), both SHARING the same interface of the mcu (address + data).
I've been looking for layout recomendations, but only found some papers from Intel, focused on motherboards with RAM slots, or datasheets from other manufacturers with very vague information. I'm sort of worried about length matching, topology and line termination, specially for the bidirectional data bus termination. Does anybody have any hints or experience with these kind of interfaces?
Some more information:
The fastest edges are produced by the RAM chip (0.8ns) so they could produce some ringing, not worried about the microcontroller or the flash outputs. At the moment, I've placed series termination resistors in all lines (address + data + control lines) and since the data bus is bidirectional and the fastest edges come from the RAM chip, I'm placing those termination resistors near that output, rest of resistors are near the microcontroller outputs. I'm using the Y topology, keeping the branch lengths as short as possible.
Thanks for the help!
robertferanec , 09-03-2015, 08:11 AM
@faluco do you have a screenshot of your placement? Your approach seems to me right, I am just not sure where are you placing the data series termination resistors - are they in the Y branch or are they in the main track?
faluco , 09-03-2015, 11:13 AM
I've done a basic drawing in paint, hope it's clear enough
The data termination resistors are placed in the main branch but just before the split so that they are nearer to the RAM chip than to the MCU. For the address bus, the resistors are on the output of the MCU. I've placed resistors on every line, maybe this is overkill?
The data termination resistors are placed in the main branch but just before the split so that they are nearer to the RAM chip than to the MCU. For the address bus, the resistors are on the output of the MCU. I've placed resistors on every line, maybe this is overkill?
robertferanec , 09-03-2015, 01:19 PM
@faluco what is part number of the memory chip? I am thinking, maybe better way could be to place it in series:
CPU --- RES ----------------- FLASH --- RAM
This way, 90MHz would go between CPU and RAM (no stub), and 30MHz would travel between CPU + FLASH + a small stub.
I am thinking if I have ever seen a design with series termination resistors close the the Memory chip - it is possible, but it is not the usual way to do it. I understand why you would like to place them this way, but maybe there is a different way to make the edges of the RAM slower (I don't know ... e.g. maybe a slower variant of the memory chip exists, ...?). Possibly, try to simulate the signal with different placement and buffers. It would be interesting to see the differences.
The main thing why I would place the components in series is, that even you create Y, only one of the chips is always active as an output and there is always only one receiver, so there always will be a stub.
CPU --- RES ----------------- FLASH --- RAM
This way, 90MHz would go between CPU and RAM (no stub), and 30MHz would travel between CPU + FLASH + a small stub.
I am thinking if I have ever seen a design with series termination resistors close the the Memory chip - it is possible, but it is not the usual way to do it. I understand why you would like to place them this way, but maybe there is a different way to make the edges of the RAM slower (I don't know ... e.g. maybe a slower variant of the memory chip exists, ...?). Possibly, try to simulate the signal with different placement and buffers. It would be interesting to see the differences.
The main thing why I would place the components in series is, that even you create Y, only one of the chips is always active as an output and there is always only one receiver, so there always will be a stub.
faluco , 09-03-2015, 02:13 PM
Hello Robert! The part number of the RAM chip is IS42S32800D-7TL and STM32F429BIT6 for the MCU.
I agree that placing the resistor closer to the memory is indeed uncommon, i just did it because looking closer to the datasheet, it can produce edges of 300ps (p.16 of datasheet, transition time). Using the fly-by topology you suggest is nice because the RAM would not have a stub, the only thing is the resistor is farer away from the output.
I've simulated both topologies with the IBIS models of the components and it produces an insane amount of ringing with very short tracks (20mm) when driving the ram data outputs. The parasitics of the MCU pins seem to be quite high so when the signal arrives to the input pin of the MCU it starts to get reflected, but I'm not sure if I should really trust this. I've been looking at board images with SDR RAM and many of them don't even terminate the signals. Also i've looked to a reference design of a board that uses this interface, although the MCU is in a BGA package instead of LQFP as mine, and it has data tracks as long as 160mm!
I agree that placing the resistor closer to the memory is indeed uncommon, i just did it because looking closer to the datasheet, it can produce edges of 300ps (p.16 of datasheet, transition time). Using the fly-by topology you suggest is nice because the RAM would not have a stub, the only thing is the resistor is farer away from the output.
I've simulated both topologies with the IBIS models of the components and it produces an insane amount of ringing with very short tracks (20mm) when driving the ram data outputs. The parasitics of the MCU pins seem to be quite high so when the signal arrives to the input pin of the MCU it starts to get reflected, but I'm not sure if I should really trust this. I've been looking at board images with SDR RAM and many of them don't even terminate the signals. Also i've looked to a reference design of a board that uses this interface, although the MCU is in a BGA package instead of LQFP as mine, and it has data tracks as long as 160mm!
robertferanec , 09-03-2015, 10:17 PM
What is the FLASH part number?
robertferanec , 09-03-2015, 10:30 PM
@faluco How did you simulate it, do you have some pictures / screenshots?
faluco , 09-04-2015, 01:18 AM
The flash part number is S29GL512S10TFI010.
Sure Robert! I will post later today some screenshots showing the setup and the results I obtained. In the meanwhile, do you have any other recommendations about length matching for this interace, specially relationship between CLK and rest of signals?
Sure Robert! I will post later today some screenshots showing the setup and the results I obtained. In the meanwhile, do you have any other recommendations about length matching for this interace, specially relationship between CLK and rest of signals?
robertferanec , 09-04-2015, 02:49 AM
What is the IO voltage you use? I am playing with simulation in Altium, it's fun 
faluco , 09-04-2015, 03:27 AM
Oh!
It's +3V3.
It's +3V3.
robertferanec , 09-04-2015, 11:41 AM
I played with Altium Simulator, but I am not 100% sure about it's results, so I decided to change simulator. I had to ask friend of mine to simulate it for you. Here are some results - no guarantee
The optimum case
Placing series termination resistor close to the SDRAM, setting up MEMORY as Output (green color), routing all the branches same length
The optimum case
Placing series termination resistor close to the SDRAM, setting up MEMORY as Output (green color), routing all the branches same length
faluco , 09-04-2015, 04:04 PM
Thanks for the time taken to do this!
The star topology simulation has very interesting results! What was the track length of the star's branches?
These are the results I'm getting, using the the same layout you posted above and with the 47R resistor:
1) fly-by topology (black:MCU, red:flash, green:ram):
2) star topology (same colors) (The branches of the simulated star measure 20mm):
Looking how bad things get with long tracks, I have no idea how older motherboards worked with this kind of memory
The star topology simulation has very interesting results! What was the track length of the star's branches?
These are the results I'm getting, using the the same layout you posted above and with the 47R resistor:
1) fly-by topology (black:MCU, red:flash, green:ram):
2) star topology (same colors) (The branches of the simulated star measure 20mm):
Looking how bad things get with long tracks, I have no idea how older motherboards worked with this kind of memory
robertferanec , 09-05-2015, 12:06 AM
Fantastic! Your pictures are pretty similar to ours. It's a very interesting example of showing up, that it really matters how you route the tracks. Each branch length in our simulation was 30mm long. What I am not sure about is, if or how to include the length in the package when you will be doing the layout.
@faluco please, would it be possible to send me Schematic Symbol & PCB Footprint of the three components? I would like to try to simulate it also in Altium and I would need the full component to be able to assign the IBIS model to it. BTW, for simulation I didnt use the exact model of IS42S32800D-7TL, I used the one with smaller memory size (IS42S16800F) because IS42S32800D IBIS didn't give me option to set data pin as input (I am not really sure what was the reason do not include input pin in the IBIS model). What model did you use or how did you set the "Technology" type in Altium?
@faluco please, would it be possible to send me Schematic Symbol & PCB Footprint of the three components? I would like to try to simulate it also in Altium and I would need the full component to be able to assign the IBIS model to it. BTW, for simulation I didnt use the exact model of IS42S32800D-7TL, I used the one with smaller memory size (IS42S16800F) because IS42S32800D IBIS didn't give me option to set data pin as input (I am not really sure what was the reason do not include input pin in the IBIS model). What model did you use or how did you set the "Technology" type in Altium?
faluco , 09-05-2015, 05:38 AM
Sure Robert! The forum doesn't allow me to upload the library, so I've sent it to your email.
This is my setup, so you can do it the same way as me: I simulated the DATA0 signal, the ram chip is the output and the flash and mcu are set as inputs.
The DATA0 signal is assigned to the following pins:
1) MCU: pin PD14 (no.116)
2) flash: pin no.35
3) ram: pin no.2
In theory when you import the IBIS file, you should pick the model that is assigned to the pin you want to simulate, for the MCU pin no.116 I used io8p11_arsudq_ft, io_mv for the flash pin and I/O for the ram chip. Each IBIS file contains a collection of models, you will see that each one starts with the [Model] syntax.
Basically, for 3-state pins, there's also an enable signal that you have to enable to make the model work as an output, otherwise it will be Z and it'll be set as an input. For example, in the MCU ibis file you can find this for an IO model:
Model_type I/O
Polarity Non-Inverting
Enable Active-Low
That enable signal is set to active low, so when you set it to 0 the model will behave as an output, otherwise as an input. Unfortunately I haven't done my simulations with Altium, but i can try to set it up and see if I can make it work.
Comparing the ibis files of both ram chips (IS42S16800F vs IS42S32800D) i see this big difference:
32800D:
[Model] I/O
Model_type 3-state
Polarity Non-Inverting
Enable Active-High
vs
16800F:
[Model] I/O
Model_type I/O
Polarity Non-Inverting
Enable Active-High
Maybe altium does not like the 3-state line in Model_type, you could try editing that line and set it to I/O and see if you can make it work as an input too.
This is my setup, so you can do it the same way as me: I simulated the DATA0 signal, the ram chip is the output and the flash and mcu are set as inputs.
The DATA0 signal is assigned to the following pins:
1) MCU: pin PD14 (no.116)
2) flash: pin no.35
3) ram: pin no.2
In theory when you import the IBIS file, you should pick the model that is assigned to the pin you want to simulate, for the MCU pin no.116 I used io8p11_arsudq_ft, io_mv for the flash pin and I/O for the ram chip. Each IBIS file contains a collection of models, you will see that each one starts with the [Model] syntax.
Basically, for 3-state pins, there's also an enable signal that you have to enable to make the model work as an output, otherwise it will be Z and it'll be set as an input. For example, in the MCU ibis file you can find this for an IO model:
Model_type I/O
Polarity Non-Inverting
Enable Active-Low
That enable signal is set to active low, so when you set it to 0 the model will behave as an output, otherwise as an input. Unfortunately I haven't done my simulations with Altium, but i can try to set it up and see if I can make it work.
Comparing the ibis files of both ram chips (IS42S16800F vs IS42S32800D) i see this big difference:
32800D:
[Model] I/O
Model_type 3-state
Polarity Non-Inverting
Enable Active-High
vs
16800F:
[Model] I/O
Model_type I/O
Polarity Non-Inverting
Enable Active-High
Maybe altium does not like the 3-state line in Model_type, you could try editing that line and set it to I/O and see if you can make it work as an input too.
robertferanec , 09-05-2015, 06:04 AM
Yes, that is exactly the thing. I was able to set it up as a 3 state pin, but I could not simulate it as an input. The big question is: "Is there a reason why they did the model this way or it's just inaccurate?". For example, if the chip is not enabled, does it mean, that all the data lines are in HiZ? Because that could influence the simulation. Also, when the 32800D is reading, how do I then set it up as an input?
Thank you very much for the components
Thank you very much for the components
faluco , 09-05-2015, 07:02 AM
Looking at the ibis files for the IO pins of the mcu and the flash chip they both set the model_type to I/O, so I would change that line for the ram chip aswell, could be a mistake from the manufacturer. Yes, when the chip select is disabled, all data lines are set to HiZ.
Without modifying the ibis file I managed to simulate the ram chip as in input with altium setting the ram chip pin as Tri/In with input model: I_O_tp_tri.mac and output model: I_O_tp_out.mac. Is this what you did?
Without modifying the ibis file I managed to simulate the ram chip as in input with altium setting the ram chip pin as Tri/In with input model: I_O_tp_tri.mac and output model: I_O_tp_out.mac. Is this what you did?
robertferanec , 09-05-2015, 08:24 AM
We didn't use Altium. I really wanted and I really tried, but I have really bad experience with Altium simulations - it keeps crashing all the time and I don't fully trust the results. I tried different experiments and some results are weird - of course I have to say I am not expert for simulations in Altium, so I may be doing something wrong.
For example now, I just wanted to try it again ... and I am not able to add model into the library - as soon as I click on "Add Signal Integrity" Altium keeps crashing and crashing and crashing .... even after I switched off and switched on the software
For example now, I just wanted to try it again ... and I am not able to add model into the library - as soon as I click on "Add Signal Integrity" Altium keeps crashing and crashing and crashing .... even after I switched off and switched on the software
faluco , 09-05-2015, 09:15 AM
I didn't do my simulations with altium either, but gave it a try to see if I could do the simulation which you were having problems.
Yes exactly! I had the same results. If I imported an ibis model from the signal integrity window, for the mcu case it would start crashing getting millions of crash popups, very annoying. I had to add it directly to the schematic symbol. For the ram ibis i had to manually edit it because altium was complaining about something weird.
In any case, you may be able to use the component library I sent you and then export a test board to a better simulator like hyperlynx or similar, this is what I do.
Yes exactly! I had the same results. If I imported an ibis model from the signal integrity window, for the mcu case it would start crashing getting millions of crash popups, very annoying. I had to add it directly to the schematic symbol. For the ram ibis i had to manually edit it because altium was complaining about something weird.
In any case, you may be able to use the component library I sent you and then export a test board to a better simulator like hyperlynx or similar, this is what I do.
robertferanec , 09-05-2015, 12:45 PM
I will try Thank you @faluco
Thank you @falucofaluco , 09-09-2015, 02:26 PM
Robert, do you have any experience or information about doing a timing budget analysis for the sdram signals?
robertferanec , 09-09-2015, 11:51 PM
@faluco is not hyperlynx ddr simulation offering that? To simulate ddr I normally recommend to use Hyperlynx DDRx wizard - passing that simulation is usually enough to feel confident about the layout.
faluco , 09-10-2015, 01:14 AM
I don't have access to Hyperlynx, I did the previous signal integrity simulations with a different software :\
Basically the budget consists on taking the setup and hold times of mcu and ram and with the help of a spreadsheet or similar you calculate the min and max lengths of the tracks in relation to the clock. This is important to see if the clock track needs to be lengthened with respect to other tracks to agree with the timing constraints.
Basically the budget consists on taking the setup and hold times of mcu and ram and with the help of a spreadsheet or similar you calculate the min and max lengths of the tracks in relation to the clock. This is important to see if the clock track needs to be lengthened with respect to other tracks to agree with the timing constraints.
robertferanec , 09-10-2015, 01:29 AM
I do not have any SDRAM length matching requirements, but I would say there is probably something on the Internet e.g. Hardware Tips for Point-to-Point System Design: Termination, Layout, and Routing. Have a look around, I am sure you will find something helpful.
faluco , 09-10-2015, 07:00 AM
Thanks Robert! I will take a look. There's no so much about it, many of the references are about DDR, it seems the SDR technology is a bit obsolete
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