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Forum / Schematic Design & PCB Layout / First project Design Review

First project Design Review

A_NO_ONE , 05-08-2026, 11:52 AM

Hello, I'm looking for someone who could do a design review on my PCB project. It's been in the working for on and off for around roughly half a year.

The general premise around this PCB is that it's an ESP32 Dev Board Copy (w/ no wifi) with addressable LEDs in a chain all within a small form factor.

I have a couple concerns with my project with power routing, DRC, and ESD Protection.

Here is my Git for those who want to take a look at it.
https://github.com/Hhhh-Pain/Phone-Charm/tree/main

I have provided .cad/.dsn formats as well as the bom and gerber files if needed.

For stackup it is as follows:
0.035mm for all (4) copper layers, 0.21336mm for Dialectric 1 & 3, and 1mm for Dialectric 2

For DRC rules, I am following PCBWay's Advanced specifications. I concluded that my board would be decently crowded (trace wise) early on in the project and almost all of the tracks are 1mm / 2mm wide. The vias are all through-hole, so no buried or blind vias. Though it is more expensive, I don't think there is any way of increasing the trace size and/or the via size, so I feel like I'm forced to go this route.

A_NO_ONE , 05-08-2026, 11:53 AM

My concerns are as follows:
1) Clock/XTAL not being stable after startup because of the decoupling caps nearby
2) USB impedance is not at 90 ohms w/ stackup (USB 2.0 Standard)
3) Not sure if a double GND isolation would isolate the signal between the data lines on the back from the front (Net {U5-Dout} with the USB differential pair)
4) Pretty sure ESD Protection isn't implemented correctly; How do you implement ESD protection on a board that directly leads into a power plane?
5) The decoupling caps aren't routed properly because the entire plane would oscillate (from the linear regulator switching characteristics) and the decoupling caps wouldn't be useful during long term usage because of that.
6) DRC rules are not implemented correctly (I had some problems with KiCad's software and I'm not completely sure if said rules are inputted properly)
7) Anything else I wouldn't have known because I don't know and/or I wouldn't have thought about during the entire design process.

, 05-08-2026, 11:53 AM

🤖 In the meantime, here’s a response from the [FEDEVEL AI HW Assistant]().
It helps to find relevant resources for your question, but it may make mistakes as it’s still in early development.

This is the response from the AI Assistant:
Let's address your concerns systematically using insights from hardware design best practices and the video resources available:

**1. Clock/XTAL Stability**
- Decoupling caps near crystal are good practice, but ensure:
- Caps are placed as close as possible to XTAL pins
- Crystal traces are kept short (<10mm) and symmetric
- Ground guard ring around crystal area helps
- Avoid routing other signals near crystal (observed in your layout)

**2. USB 2.0 Impedance**
- Your 4-layer stack (0.035mm Cu, 0.213mm dielectric) needs controlled impedance:
- Use JLCPCB's impedance calculator [like shown here](https://www.youtube.com/watch?v=KWIzhbQaZZk&t=19510)
- For 90Ω differential:
- Target 6mil trace width with 8mil spacing (adjust based on exact dielectric constant)
- Keep differential pairs on same layer without vias

**3. Ground Isolation**
- Double ground isolation between USB data lines and LED signals isn't recommended:
- Maintain continuous ground plane under high-speed signals
- Use 3W rule (trace spacing = 3x trace width) between sensitive signals
- Group digital/RF/analog sections instead of splitting ground

**4. ESD Protection Implementation**
- Critical issues observed:
- ESD diodes must be placed <5mm from USB connector [as shown here](https://www.youtube.com/watch?v=rmuxsm1bEr0&t=2355)
- Route ESD protection directly between connector pins and ground (not through power plane)
- Use TVS diodes with <1pF capacitance for USB 2.0
- Ensure clamping voltage < IC's maximum withstand voltage

**5.

, 05-08-2026, 11:53 AM

Decoupling Capacitors**
- Your linear regulator (AMS1117) needs:
- Input/output caps within 2mm of regulator pins
- Bulk capacitor (10μF) near power entry
- 100nF MLCC in parallel with 1μF near ESP32
- Star routing for power distribution

**6. DRC Implementation**
- Critical checks to perform:
- Minimum clearance: 0.2mm (8mil) for power traces
- Annular ring: >0.15mm
- Via size: ≥0.3mm drill/0.6mm pad
- Differential pair length matching: <150mil mismatch

**7. Additional Recommendations**
- LED Chain Considerations:
- Add series resistors (22Ω) near LED data inputs
- Keep LED data traces <100mm without termination
- Manufacturing:
- Panelize with 0.5mm mouse bites
- Add fiducials and test points
- Confirm solder mask expansion (0.05mm minimum)
- Thermal:
- Use thermal relief on LED pads
- Add ground pours under high-current LEDs

**Critical Action Items**
1. Redo USB routing with impedance control
2. Reposition ESD protection at connector
3. Reorganize power distribution network
4. Add crystal guard ring and adjust decoupling
5. Verify DRC against PCBWay's capabilities

For specific layout adjustments, I recommend watching [PCB layout best practices](https://www.youtube.com/watch?v=-luLIJqURlY&t=2498) and [ESD protection implementation](https://www.youtube.com/watch?v=rmuxsm1bEr0&t=227). Would you like me to elaborate on any specific aspect?

You can continue chatting with the AI Assistant here:
https://fedevel.com/hw-assistant

A_NO_ONE , 05-08-2026, 12:08 PM

A_NO_ONE , 05-08-2026, 12:09 PM

A_NO_ONE , 05-08-2026, 12:13 PM

XTAL - fyi, the power plane that's surrounding the crystal is also a 3v3 plane and not the typical ground plane

A_NO_ONE , 05-08-2026, 12:14 PM

and on top of that, the bottom plane (the blue one) is a 5v power plane. green and orange are both ground planes

QDrives , 05-08-2026, 03:26 PM

1) There are no decoupling caps with the crystal. You have the load capacitors there. But why the inductor? Is that because you used a 40MHz crystal and need (or prevent) 3rd overtone?
2) Got the PCB in pdf too?
3) No idea what you are talking about.
4) Are you talking about U7? Schematic is ok, layout maybe not.
5) See point 2.
6) Screenshot?
7) Definitely. See screenshot.

QDrives , 05-08-2026, 03:40 PM

I see you have some screenshots of the PCB as well.
2) Why not?
3) For USB 2 it will not be a problem.
4) Layout is not ok. Go from connector to TVS diode. Then from TVS diode onwards.
5) Decoupling caps? You mean you have not connected pin 5 of your regulator!

QDrives , 05-08-2026, 03:41 PM

Do not place 3.3V under or around your crystal.

A_NO_ONE , 05-09-2026, 03:56 AM

got it. i'll make a DRC rule around it

A_NO_ONE , 05-09-2026, 04:08 AM

1) I was talking about C20 & C16 right next to the qfn chip; oh wait. i was supposed to be a 24 ohm resistor not an 24nH inductor omg. i'll fix that up right now.

https://docs.espressif.com/projects/esp-hardware-design-guidelines/en/latest/esp32/schematic-checklist.html (R2, pin45)

2) Not really, i have the files on github that have files for KiCad but idk how to export as pdf. On top of that, I have the documentations linked with the objects on the schematic

3) okok. got it.

4) I'll change it then. is there any examples where I can reference? I am having a hard time routing the tvs diode.

A_NO_ONE , 05-09-2026, 04:11 AM

for 6 & 7