FEDEVEL
Platform forum

dangcaominh , 10-04-2025, 02:26 PM

I am designing a custom FPGA board with XC7Z015 and currently has to put gigabit ethernet to PL bank 13 because PS MIO is used up all. I had wired the VCCO13 to 1V8. However when dealing with 1V8 gigabit ethernet PHY in PS, we must use HSTL 1V8 I/O standard and an additional VREF 0v9 circuit wired to the PS. Does the same apply here, with the VREF circuit tied to bank 13?

dangcaominh , 10-04-2025, 02:28 PM

Here is the I/O planning window