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LVDS Layout

Elian Terelle , 01-04-2026, 06:25 PM
Hi, i'm currently laying out a pcb for a 3G-SDI (Video) Serializer (LMH0340), to attach to an FPGA Development Board (Mimas A7). It has 6 differential Signals that will be driven at around 300 MHz. I've just finished the length matching and will be ordering the pcb soon, but i thought i'd post it here first.

Does this look good or are there any obvious mistakes / things that could be better?

I calculated the Trace widths using JLCPCBs Impedance Calculator, for the spacing of the IC Pins.
Elian Terelle , 01-04-2026, 06:27 PM
Fusions Signal Integrity analysis reports a little bit higher impedances (108 Ohms instead of 100 Ohms) on the parallel Segments, and on the meanders low impedances of 58 Ohms. I guess this is a normal side effect of the length matching?
Elian Terelle , 01-04-2026, 06:29 PM
I know that the 2.54mm pin headers aren't ideal, but it's what my fpga board has (at least the fpga board also has length matched differential pairs to the fpga)
QDrives , 01-04-2026, 07:39 PM
1) I would place the length match encircled (boxed) closer to the pin and
2) Try to move the trace from under the IC to around it. This currently can cause a short more easily.
Elian Terelle , 01-04-2026, 09:32 PM
Ah, you're right, thanks!
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