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, 01-16-2025, 08:30 AM

I am working on a project with quite a few connectors going to several external components. I decided to be safe an isolate all of these connections each with optocouplers and isolated PSU (blue arrows).

Limitations / Restrictions:
- 4L stack-up due to budgetary constraints
- Form factor is set so I cannot change the shape of the board.
- Have to use these connectors.

This now brings up the question of the GND plane on L2. It seems frowned upon to have multiple GND sections as apposed to an "uninterrupted" GND plane. Referring to the image attached, I see no clear issue as long as I stick to routing over the appropriate GND sections only eg. All signals going to the uC should be routed over the 'system GND' pour on the L2 and not cross over a different GND or clearance area? I added some traces for reference running from the Optocoupler outputs to the uC. Both Optocoupler output and uC will have system ground as a return path.

I have added 0.5mm clearance between polygons with belonging to different NETS on L2.

QDrives , 01-16-2025, 05:04 PM

So what is your question?

, 01-17-2025, 05:14 AM

@QDrives - than k you for your response.

Whether dividing the layer into multiple different isolated GND sections is really an issue providing I only route corresponding signals on each GND section of course?

Ideally I would put all the connectors on one side or alongside the perimeter therefor simplifying the system GND plane, but unfortunately there is just not enough room to do so.

QDrives , 01-17-2025, 09:05 PM

Still not very clear to me but let me put things differently and you can confirm.
1) There is a requirement to galvanically isolate sections. Correct?
2) The Gnd layer (layer 2, below top) is split to create sections with isolated Gnd.
3) All signals travel over their reference Gnd. Only optocouplers and DC-DC converters are used to cross the splits. Do note that this is not always the case!
4) You have added a capacitor and high resistance (>= 500k ohm) resistor in parallel between the Gnds for high frequency noise and discharge of static build-up from occurring.

, 01-18-2025, 08:19 AM

Hi @QDrives

My apologies for not being clear enough.

1. This is correct. As these 'off-board items' will be connected using longer wires and might be placed in noisy AC environments (or exposed) I thought to best to isolate them rather than just protect them with eg. TVS diodes.

2. Yes indeed, GND is on layer two. I am trying to do all routing in L1. Might need to use L3 for **some** routing in more densely pack areas but it will not be in the isolated sections as these are easy enough to do on L1.

3. This is correct. No trace will either cross split area or different reference GND.

4. In was hoping not to do this in order to maintain galvanic isolation as I need to meet Intrinsic safety standards. My plan was to add a copper pour on L1 as well and stitch it to the GND on the second layer.

I will also be adding stitching vias around the periphery of the isolated GND sections.

Thank you for the assistance, it is much appreciated!

QDrives , 01-18-2025, 05:24 PM

1. What you write does not imply "required" nor do I think isolation helps here. Beter to apply differential signaling. You also still need protection eg. TVS diode.
3. No mention where it is not the case.
4. You still have even with the capacitor and resistor. Do note that EMC is also required for safety and these components are for EMC.

, 01-18-2025, 06:46 PM

1. Just for confirmation, I have placed TVS diodes on every "line" coming in from a device connecting to the PCB. I will rather be safe that having comebacks. I can also DNP these if we find no transient spikes when testing. Are you of the opinion that isolating these inputs by means of optocouplers are not needed?

3. hhmmmm... seems I have been taught wrong then in terms of galvanic isolation. I was under the impression that there will be some leakage current regardless and true galvanic isolation is therefor not achieved. I will place Class-Y capacitors, at least of the fail, they will fail 'open'. Will place them in parallel then with maybe 1MΩ resistors.

Thank you for your patience, it is much appreciated!

, 01-18-2025, 07:03 PM

I was indeed wrong about the isolation... also found this in an article by Cadence :

*"Y-type capacitors can meet galvanic isolation requirements that ensure safety, and it is their capacitance value that controls the emissions." *

Thank you for pointing that out!

QDrives , 01-18-2025, 07:38 PM

".*..if we find no transient spikes when testing.*" -- Depends.... Do you need to do EFT and surge tests on these connections due to cable length?

, 01-19-2025, 05:41 AM

Just for our my sake... not required by client. Just a habit I picked up as I have had too many incidents in the past where components connected to inputs (whether it was FETs or GPIO had random failures once clients got their hands on it 🙂

, 01-19-2025, 05:42 AM

I requested client for a full set of external hardware so I can try and duplicate an absolute worst case installation setup.

QDrives , 01-19-2025, 06:02 PM

"*...components connected to inputs...*" -- I cannot even recall if I ever have seen a digital input get damaged on designs I did.
What kind of inputs are yours?

, 01-19-2025, 06:16 PM

haha... you have clearly not clearly with South African clients 😂 I am not sure what they do, but it happens. No specific inputs, could be anything from logic level voltage inputs triggering digital pins to Analog pins.

I suspect mostly i could be due to incorrect wiring or ESD events, not sure really. So I started adding TVS diodes to anything going 'off board'.

, 01-19-2025, 06:18 PM

I always though it is best practice to implement galvanic isolation where there is no clear guideline of cable lengths that will be connecting to the PCB or where connected devices can reside in noisy environments. Is this a flawed assumption?

QDrives , 01-19-2025, 06:19 PM

"*...Logic level...*" -- I hope that signal does not go directly into a logic IC? That could damage it.
You should check with TVS diodes what the maximum voltage is at high current. (hint).

, 01-19-2025, 06:20 PM

in my early days.... yes it did go to eg. the uC. 😱

, 01-19-2025, 06:20 PM

but that was a ling time ago, hehe

, 01-19-2025, 06:22 PM

In this case some of the I/O going off-board are connected to iductive loads eg. Solenoid valves or coils. Hence the idea to add the TVS's at the connector on the PCB and also adding the optocoupler. If there is some kickback that somehow get's passed the TVS, at least it will only damage the optocoupler and not anything else on that board?

, 01-19-2025, 06:24 PM

so the idea behind all the isolation is that anything connecting to one of the two uC's has the same voltage supply and GND as the uC's.

QDrives , 01-19-2025, 06:28 PM

For solenoids, coils and other inductive parts you need to add freewheeling diodes.
If you do not know the 'polarity' than add a snubber circuit.
Here is a robust input circuit.

, 01-19-2025, 06:29 PM

Thanks!

QDrives , 01-19-2025, 06:30 PM

The 2k2 and transistor you can get into a single package.
https://www.digikey.nl/en/products/filter/transistors/bipolar-bjt/single-pre-biased-bipolar-transistors/292

QDrives , 01-19-2025, 06:30 PM

The 10k pull-up can be in the MCU. All in all 4 components.

, 01-19-2025, 06:31 PM

Thanks!! Appreciate the advice!

, 01-19-2025, 06:33 PM

are you based in the Netherlands?

QDrives , 01-19-2025, 06:33 PM

Yes I am.

, 01-19-2025, 06:39 PM

The first person I "meet" closer to home.... it has always been US based contacts.

Here is how I am dealing with inputs from encoders, it has served me well in the the past. Seems my reasoning was flawed?

The voltage driving the encoder originates on the PCB and is supplied by a small isolating DC-DC psu.

, 01-19-2025, 06:41 PM

wire length from the connector on the PCB (insider fireproof section) to the encoder (on 240VAC pumps) is about 1m.

QDrives , 01-19-2025, 09:13 PM

Well, I would not consider the Netherlands much closer than the US.

I often did encoders with opto-couplers too.
With 5V, 560ohm and ~1.6V Vfwd you get about 6mA.
The rare problems with inputs were encoder inputs set to 5V but driven by 24V. The product could do both, but the switch should have been set to the right position.
The problem encountered was a highly overloaded resistor and in some cases that was fatal. So make the resistors bigger (0805 or 1206).

With 1m there is no need to do surge testing.

What is the pulse frequency of the encoder?

, 01-20-2025, 10:10 AM

Well... at least it is the same time zone 🙂

These are driven with 5V that will originate on this PCB... so worse case I suppose is that they will have it set to 12V or 24V and it will not work.

I use both 0805 or 1206 on optocouplers, especially when using AC optocouplers.

My reasoning for isolating everything has mainly to do with protecting the GPIO on the Micros against Human error or hopefully eliminating any possible noise that could have coupled onto the circuits. I have seen clients taping non shielded 3V3 signal and analog wires to 240VAC cables.

QDrives , 01-20-2025, 07:54 PM

"*I have seen clients taping non shielded 3V3 signal and analog wires to 240VAC cables.*" -- Then I would increase the gap between the two section to at least 1mm.
And make sure that the DCDC and opto have handle >= 500V isolation.