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Karan paliwal , 01-11-2026, 05:42 PM

I am calculating the impedance of the IWR6843AOPEVM PCB using the available layout and stackup information. However, when I calculate the impedance based on the layout parameters using Altium Designer’s Impedance Profile, the calculated impedance does not match the expected impedance of the reference PCB.

Could this mismatch be due to the limitations of impedance calculators, such as the use of nominal dielectric constants, simplified field solvers, and the absence of fabrication-specific parameters like copper roughness, solder mask effects, and actual dielectric thickness after lamination?

Additionally, is it correct to assume that the impedance of a fabricated reference PCB cannot be accurately reverse-calculated using layout dimensions alone, and that the original design impedance was likely tuned using the PCB manufacturer’s field solver or post-fabrication measurements?

(we are using the PCB version SPRR418A (G version).
https://www.ti.com/lit/zip/SPRR418

Is it possible that the impedance-related details provided for this PCB are incorrect?
I am facing difficulty matching the differential pair impedance based on the given stackup and layout information.
Could you please help me calculate and understand the differential pair impedance for this PCB or for the given stackup?
Additionally, if I want to set up an accurate impedance profile for this PCB, could you please guide me on how to define it correctly?

@QDrives @Robert Feranec

QDrives , 01-11-2026, 09:29 PM

There are 2 things that make the impedance calculation differ and is usually 'forgotten':

1) Traces are **not** 'square'. Trapezoidal is a better name, but that is not entirely correct either.
As you can see in this Altium screenshot, you can adjust the parameters to go from square to trapezoidal.

2) Prepreg is used to make the boards. That prepreg, or better the resin, fills the gaps between the traces. Or it fill the gaps of antipads when on a (Gnd) plane / polygon.
This makes the prepreg layer just a tiny bit thinner. But that tiny bit, does alter the impedance.

Copper roughness, as seen in the lower part of the screenshot, has an influence on the losses, not so much the impedance.
Soldermask does impact the impedance. The thickness and Dk should be assigned.
Fabricators sometimes adjust the width of traces to match the impedance required. More expensive, but possible.


I see that the IWR6843AOPEVM mentioned "60 GHz". Then FR4 would not be a proper material.
You do not want solder mask over the traces, but for instance EPIG (not to confuse with ENIG or ENEPIG).
How long are the traces for this frequency?

Karan paliwal , 01-12-2026, 02:54 PM

I am calculating the differential impedance of the differential pair class defined in the TI IWR6843AOPEVM PCB layout. However, when I use the same trace width, spacing, and stackup parameters in Altium’s impedance calculator and Saturn PCB Toolkit, the impedance does not come out to 90 Ω.

Karan paliwal , 01-12-2026, 02:56 PM

I am not able to understand how to approach this properly. Since the schematic and PCB layout in this design are not properly synchronized, I am facing difficulty in understanding the concept. Could you please suggest a reference PCB that I can refer to for a proper understanding? This would be very helpful for me.

QDrives , 01-12-2026, 03:53 PM

So what do you get?
What data do they provide?

Karan paliwal , 01-13-2026, 04:04 PM

To clearly explain my approach and ensure that I am able to describe the issue correctly, I am outlining the steps I followed below.

I reviewed the PCB layout available in the TI reference design package SPRR418 (G version) from the following link:
https://www.ti.com/lit/zip/SPRR418

Step 1:
I opened the G version PCB layout included in the SPRR418 package and identified the USB differential pair traces, which are intended to be routed as a 90 Ω differential pair.

Step 2:
In the PCB layout, I highlighted the USB differential pair using the Altium filter query:
InDifferentialPairClass('90E')

Step 3:
I also verified that this USB differential pair is explicitly defined in the Differential Pair Routing rules, where parameters such as minimum trace width and minimum gap are specified.

Step 4:
I used the same trace width, spacing (gap), and available stackup parameters from the SPRR418 G version layout and entered these values into:

Altium Designer’s Impedance Profile, and

Saturn PCB Toolkit for manual impedance calculation.

Step 5:
However, using these same parameters, the calculated differential impedance does not result in 90 Ω in either Altium or Saturn PCB Toolkit.

I am attaching images of the calculated values and settings I used for the impedance calculation. Kindly review them and let me know if there is any mistake in my calculation approach or assumptions.

Due to this mismatch, I would like to understand how the 90 Ω differential impedance was achieved in the SPRR418 G version reference PCB.

Karan paliwal , 01-13-2026, 04:11 PM

for Sig2 layer

QDrives , 01-13-2026, 09:15 PM

The most important layer to look at is Sig2 as 90%+ is on that layer.
There you have an impedance of ~87Ω. That is well within the 10% tolerance of 90Ω.

Karan paliwal , 01-14-2026, 01:54 AM

But in bottom layer its 78 ohm

QDrives , 01-14-2026, 08:26 PM

Trace length? Rise time?
Copper thickness? Solder resist thickness? Pressed prepreg thickness? Effect of Dk on pressed PCB?
Then there is the series terminator...