FEDEVEL
Platform forum

Bob , 09-27-2025, 07:25 PM

overview: FC, RPI CM5, ~6-layer PCB, mixed high-speed (PCIe, ETH, USB) + high-current (absolute max designed for 13A)
I just finished a rough design sketch of the board to have a feel for where everything goes
Now im just starting layout and want to think ahead when choosing my stackup and think of how i want to implement Power and Highspeed stuff
the stackup i have in mind rn is:
L1: Signals
L2: Solid GND
L3: Segmented POWER planes (+5 V, +3V3, +1V2, VBAT, etc.)
L4: Highspeed / critical
L5: GND
L6: Bottom – power entry, high-current DC distribution (im not sure about this)

What are your thoughts and advice and what are the main things i should keep in mind for? I'm relatively new to layout so any good relevant resources/articles/videos would be greatly appreciated!

Thanks in advance :)

QDrives , 09-28-2025, 04:14 PM

Stack-up looks acceptable, but you have a 'reverse build-up' (cores on the outside).
You may want to change the outer prepregs to 2x1080, which gives you about 0.16mm or 6mil.
Also your cores can drop to about 0.2mm (or 8 mil).
Your center prepreg (optionally a 'fake core') will remain 4x7628, so about 0.8mm or 30 mil.
That will make the coupling to the Gnd layers a little better.
This also makes the board just a little bit lighter which is beneficial for flight.

tomas.kaplan , 09-29-2025, 07:50 AM

I would take really good care while you are routing your highspeed signals on L4. It should be coupled to L5's GND but still, i would avoid routing big power planes of switched mode power supplies near the high speed signals.

Other option would be to use TOP layer for your highspeed routing (if components placement allows it) and route your general purpose signals on L4.

Also, put GND via next to each signal via if you are switching your reference planes. E.g. going from L1 to L4. Thats very important.

Bob , 09-29-2025, 12:51 PM

makes sense ill be doing this

Bob , 09-29-2025, 12:56 PM

i should def keep this in mind
the main challenge rn is my super tight usable space on L1, like im starting with layout of my power circuitry where the power connectors are on L1 and im afraid there wouldnt be any space left for HS signals. another option i was thinking initially was having all the power drop immediately from L1 connectors to L6 and but all the big ICs for power there instead so L6 is shared between power entry and slow IO

Bob , 09-29-2025, 12:57 PM

thank you both for the great advice ❤️