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J , 09-05-2024, 05:42 AM

Currently, I am designing a small and compact ESC on a 8-layer 1.2mm thick PCB.

The problem that I encountered is the proper stack-up. At the moment I came up with something like this:

1. TOP -> Signal + LPWR (Low current 5V, 3V3, etc)

2. GND plane

3. Signal + LPWR (Low current 5V, 3V3, etc)

4. HPWR (Power for 3-phase inverter, Phases, etc.)

5. HPWR (Power for 3-phase inverter, Phases, etc.)

6. Signal + LPWR (Low current 5V, 3V3, etc)

7. GND plane

8. BOTTOM -> Signal + LPWR (Low current 5V, 3V3, etc)


Layer 4 and 5 will probably be the same.


I would appreciate it if anyone could have a look and let me know what you think.

Thank you very much in advance for help.

J , 09-05-2024, 06:34 AM

Between layers 3 - 4 and 5 - 6 would be thicker prepreg or even core (not sure if such configuration is possible). It will be ordered from pcbway (custom stack-up).

Artarka , 09-05-2024, 08:36 AM

Maybe have a look at this?
https://www.youtube.com/watch?v=60RxCiZuD9E

Artarka , 09-05-2024, 08:37 AM

TLDR: afaik you always want to ground (reference) plane next to each power/signal layer

Artarka , 09-05-2024, 08:37 AM

but if the product is not or commercial and you don't really care about EMC/EMI, chances are that stackup will just work fine given its small dimension

J , 09-05-2024, 08:59 AM

J , 09-05-2024, 09:00 AM

I do care about EMI. Please find above the stack-up that I came up with.

J , 09-05-2024, 09:02 AM

Thank you for sharing the video but I've already checked that. I think my case is very specific and doesn't fit in any regular solution.

QDrives , 09-05-2024, 12:11 PM

Why do you need 2x high power in the stack-up?
And 4x low voltage power?
Just call it routed power for the low voltage.
It may also be better to use thicker copper, or this all for weight reduction?

J , 09-05-2024, 12:55 PM

2x high power is to handle 10A currents. There are many vias on the way that make the high power polygons thin. Additionally, it will act as heatsink for mosfets. Thicker copper on internal layers increases the cost significantly and I don't remember but it was probably not possible to get thicker copper and 1.2mm pcb thickness for 8 layer design.

J , 09-05-2024, 12:58 PM

Regarding 4x low power it is mainly because of signal tracks. It is not possible to finish the design on 2 or even 3 signal layers. 4 are necessary. Because of that I cannot use one of these LPWR internal layer for power only

QDrives , 09-05-2024, 02:25 PM

Thick copper expensive? I would expect 8 layers and thin cores be more expensive.
But if you care about cost, EMI should be higher priority.

J , 09-05-2024, 02:43 PM

Yes, the 1.5oz thick copper on inner layers doubles the cost :/ 2oz is not available for this stack-up.

Robert Feranec , 09-06-2024, 02:10 PM

I forgot the main reason, but PCB manufacturers don't like thick copper on inner layers. I think, one of the reasons may be, that then a lot of resin from prepreg will flow into the spaces between the tracks ... and this may be a problem.

J , 09-06-2024, 02:35 PM

Thank you for your reply. What do you think about the stack-up? I uploaded a screenshot from altium stack-up configuration.

QDrives , 09-06-2024, 07:37 PM

You do have to keep that in mind.
I am currently working on a 6 layer board with 105um (3oz) for all layers. No problems, but then my thickness is closer to 2.0mm

Robert Feranec , 09-07-2024, 06:46 AM

I have never used 63um dielectric. are not 50ohm traces than too narrow?

J , 09-07-2024, 08:43 AM

@Robert Feranec Thank you for pointing it out. I agree it was not good, the tracks on inner layers would have to be about 3mils even slightly less. I increased the core thickness between layers 2-3 and 6-7 to 3mils. I am uploading the altium stack-up configuration again. I think it is much better now and total pcb thickness is 1.22mm so it is still accepted. Could you have a look on it one more time?

J , 09-07-2024, 08:43 AM