FEDEVEL
Platform forum

User , 03-23-2025, 03:30 PM

Hello, will this routing cause assembly issues? I try providing thick traces on power and gnd pins, I was told by someone it WILL fail assembly, and that I should reliy on thermal reliefs only

QDrives , 03-23-2025, 03:35 PM

This should not fail assembly.
But it will fail fabrication as the opening in copper in the green highlighted section is to small.

User , 03-23-2025, 04:11 PM

How do you know it is too small?

User , 03-23-2025, 04:13 PM

0.45mm in the Y axis

QDrives , 03-23-2025, 07:30 PM

I doubt the opening is 0.45mm in Y axis.
**If** this is a SO16 with 1.27mm pitch, the pads would be something like 0.65mm.
The opening is about 1/4 of the pad width so 0.16mm.
However, I started with "if" and pad width to space ratio makes it more like a TSSOP with 0.65mm pitch so that the opening would be more like 0.08mm.

User , 03-23-2025, 08:13 PM

User , 03-23-2025, 08:14 PM

Which opening are you talking about? Is is the 0.075mm one?

QDrives , 03-23-2025, 09:03 PM

Yes, especially the 0.075mm one.
Depending on the copper thickness, the 0.15mm could also be a problem.

User , 03-23-2025, 09:06 PM

So, would the best be to rely on thermal relief only ? I tried to make my pcb design copper pour agnostic by routing gnds connection,and making them lower impedance at the same time

QDrives , 03-23-2025, 09:12 PM

"*So, would the best be to rely on thermal relief only ?*" -- That depends. What is it you want / need to accomplish?
Better place vias closer to the Gnd connection of your capacitors.

User , 03-23-2025, 09:52 PM

I want to lower the impedance between my GND pins and the GND plane underneath

User , 03-23-2025, 09:53 PM

I use a gnd Plane on the layer below as well as copper pour on the same layer as the component

QDrives , 03-23-2025, 10:02 PM

Ok, but why do want to decrease the impedance? Are you communicating (seeing MOSI) at GHz frequency?
Do not get me wrong, there is no problem adding (wider) traces and multiple vias to pins.
Just keep an eye on the fabrication and assembly.
Why not route pin 8 like pin 9?

User , 03-23-2025, 11:16 PM

No particular reason,just want the best grounding for the chip, I can route it like pin 9 indeed

User , 03-23-2025, 11:17 PM

To what should I pay attention on the way I connect pins for good assembly? I don't have much experience with dfm

QDrives , 03-23-2025, 11:55 PM

https://www.youtube.com/watch?v=XumNc480qYo

QDrives , 03-24-2025, 12:00 AM

As for DfX (DfM, DfA, DfT, etc.) there are many rules. Too many for me to write here.
Some are 'hard' (trace width, clearance, etc.) some are 'soft' (distance of via from pad, etc.)