I am having trouble getting ModelSim up and running to support some HDL work that I have been doing. It is likely the result of operator error -- I used ModelSim for some Xilinx based projects a few years ago so I have some familiarity, but am brand new the the Altera/Quartus environment and am definitely rusty when it comes to the process so I appreciate your patience.
For starters, I am getting an error when running ModelSim on a clean bladeRF project (hosted, 115KLE). After cloning, building, and opening the project in Quartus, I run the RTL Simulator and see the following log output once ModelSim launches:
Code:
// other stuff # -- Compiling architecture hosted_bladerf of bladerf# ++ Error: (vcom-11) Could not find work.bladerf# ++ Error: ~/Documents/bladeRF/source/hdl/fpga/platforms/bladerf/vhdl/bladerf-hosted.vhd(27): VHDL Compiler exiting# ++ Error: ~/altera/13.1/modelsim_ase/linuxaloem/vcom failed.# Error in macro ./hosted_run_msim_rtl_vhdl.do line 68# ~/altera/13.1/modelsim_ase/linuxaloem/vcom failed.# while executing# "vcom -2008 -work work {~/Documents/bladeRF/source/hdl/fpga/platforms/bladerf/vhdl/bladerf-hosted.vhd}"ModelSim>
As I mentioned this is on a stock project, so I suspect it could be a configuration or path problem. I know the *_tb.vhd and *.vho files are spread out throughout the project tree, so is there a certain directory I should be in when doing this? Once I get up and running with these stock bladeRF testbenches I can apply that configuration to my own application. Please let me know if I can provide any additional information. Thanks!
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Thanks for any help given.