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VanBudd , 06-21-2021, 04:51 AM

Hello everyone,

Im planning a project and want to ask which Layerstack you would choose.
Ive made a first working prototype with IMX6ULL SoM and 4 Layers.
Next step would be to integrate the IMX with RAM, eMMC and PMIC.

The PCB contains:
- IMX6ULL
- 512mb DDR3 RAM
- 8GB eMMC
- PMIC
- 2x Ethernet 100Mbps
- 2x USB2.0
- RS485
- RS232
- CAN
- 2.4GHz Zigbee/BT
- 868MHz wireless M-Bus

PCB is around 90x70mm.


My idea would be a 8-Layer Stack

- Signal
- GND
- Signal
- Power
- GND
- Signal
- GND
- Signal

Is one Power Layer enough?
What do you think? It should pass EMC testing.

Lakshmi , 06-21-2021, 08:14 AM

For the processor board, you will need at least 2 Power planes. I think you can go with 10 Layers adding power planes.
Have a look at the reference design board or EVAL board and see how they have managed the power plane.

robertferanec , 06-26-2021, 01:50 AM

I agree with @Lakshmi. I also see 1 power plane as a possible problem. I am not sure how the pinout of ULL is looks, but often there are crossing power planes under CPU and they only can be routed on two layers (at least).

VanBudd , 06-26-2021, 01:52 AM

Thank you very much for your answer!

If the distance between Layer 3 (Signal) to Layer 2 (GND) and Layer 6 (Signal) to Layer 7 (GND) is much smaller then the distance to Layer 4 and 5 can i go with Power on Layer 4 and 5?
So the reference plane for the signallayers should be the outer GND Layers.

- Signal
- GND
- Signal
- Power
- Power
- Signal
- GND
- Signal

Or should i go with Roberts 10-Layer stack with four Powerplanes?
I have no HDMI, SD, PCIe etc. So i need only 5V, 3V3 and the processors power, which i think is VDD_DDR3, VDD_SOC and VDD_ARM (please correct me if im wrong).
So do you think two Powerplanes will be enough ?

VanBudd , 06-26-2021, 01:55 AM

Thank you very much for your answer!
So i should go with your 10-Layer stack which you also use in OpenRex project?

VanBudd , 06-26-2021, 02:42 AM

The evaluation board only have 4 Layers
https://www.nxp.com/design/developme...X6ULL-EVK#t768

Thats crazy! 😲

robertferanec , 06-26-2021, 03:20 AM

- The module has 4 layers?

PS: I normally do not use 8 layer stackup - exactly because I am not very happy how to order layers there. That is why we often use 10 layers instead.

VanBudd , 06-26-2021, 03:36 AM

Yes, in the Design Files there is an allegro brd file of the SODIMM SoM with IMX6ULL where you can see the Layerstack.

robertferanec , 06-26-2021, 03:59 AM

- then maybe the chip is designed for low layer count layout. Have a look how they did it.