SDR SDRAM validation techniques
Max , 08-26-2021, 07:17 AM
Hello all,
In my design, I am using single data rate SDRAM memory attached to the DSP.
Has anyone from the forum tried or can support me on finding IEEE standards or other methods to validate the SDRAM chip. I have looked for it, but could not find anything, only for DDR3/4, but not for SDR.
So, if someone has encountered this issue, please share some thoughts on which docs, app notes
or something, have to use as a reference.
In my design, I am using single data rate SDRAM memory attached to the DSP.
Has anyone from the forum tried or can support me on finding IEEE standards or other methods to validate the SDRAM chip. I have looked for it, but could not find anything, only for DDR3/4, but not for SDR.
So, if someone has encountered this issue, please share some thoughts on which docs, app notes
or something, have to use as a reference.
robertferanec , 08-27-2021, 07:35 AM
What would you like to validate? Usually we run intensive memory test in different temperatures for hours/days on multiple boards to be sure memory is working oki.
Max , 08-27-2021, 07:45 AM
Hello Robert!
I am want to validate it against some timing diagrams. Are not there some IEEE standards or Jedec you are aware of? For example the read or write functions are supposed to follow some predefined and standardized timings defined in some standards, depending on the type of memory, frequency and so on and so forth.
I am want to validate it against some timing diagrams. Are not there some IEEE standards or Jedec you are aware of? For example the read or write functions are supposed to follow some predefined and standardized timings defined in some standards, depending on the type of memory, frequency and so on and so forth.
robertferanec , 08-27-2021, 07:48 AM
For SRAM, it is often possible to measure it (with a good oscilloscope and if you have access to the memory pins).
Max , 08-27-2021, 08:56 AM
Hello Robert!
I think it would be applicable also for Dram, but I am wondering what should I use as a reference to compare my results. So far I only have the data sheet, but will try to dig deeper,. In case there are no standards for this.
I think it would be applicable also for Dram, but I am wondering what should I use as a reference to compare my results. So far I only have the data sheet, but will try to dig deeper,. In case there are no standards for this.
robertferanec , 08-30-2021, 05:33 AM
Datasheet of the memory chip and cpu/mcu should describe the required timing parameters.
ruckb , 12-31-2021, 09:15 AM
Hello Max,
the thread is quite old already, so I'm not sure if the respons is still required. I do memory interface verification on a daily basis. Memory is speced at JEDEC, so you need a login there. JEDEC changed the policy some time ago and for current specs you need either to be member or buy them. But I think the old specs are still available for download after registration.
If you look for timings iI guess you could find some information in document 3_11_05_01R12.pdf and 3_11_06R9.pdf (guess with a search on the JEDEC site you can find this).
BTW, the interface of SDR was still LVTTL, so this might help alreadfy.
But as Robert mentioned you might take better the vendor datasheet e. g.
Regarding verification: dependent on the testpionts you could get SDRAM could be slow enough to measure (writes) with some cm distance to the DRAM. But I had a case about 2 years ago, where a new DRAM shrink caused issues.. Problem was, that with reflections the overshoots have been too high, but with any testpoint on the board it was difficult to really quantify the overshoots. For this system my customer built an interpsoer for his DRAM, just to allow measurements...
just my two cents..
Hermann
the thread is quite old already, so I'm not sure if the respons is still required. I do memory interface verification on a daily basis. Memory is speced at JEDEC, so you need a login there. JEDEC changed the policy some time ago and for current specs you need either to be member or buy them. But I think the old specs are still available for download after registration.
If you look for timings iI guess you could find some information in document 3_11_05_01R12.pdf and 3_11_06R9.pdf (guess with a search on the JEDEC site you can find this).
BTW, the interface of SDR was still LVTTL, so this might help alreadfy.
But as Robert mentioned you might take better the vendor datasheet e. g.
Regarding verification: dependent on the testpionts you could get SDRAM could be slow enough to measure (writes) with some cm distance to the DRAM. But I had a case about 2 years ago, where a new DRAM shrink caused issues.. Problem was, that with reflections the overshoots have been too high, but with any testpoint on the board it was difficult to really quantify the overshoots. For this system my customer built an interpsoer for his DRAM, just to allow measurements...
just my two cents..
Hermann
Max , 01-13-2022, 03:43 AM
Thanks for your attention and advices provide! Really helped!
ruckb , 01-13-2022, 03:56 AM
You are welcome! If you have any more specific question on the signals or the measurement I'm quite sure I can provide some hlep..
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