IMX6Q and DDR3 : The 'oups' error
Cécile , 11-12-2022, 02:32 AM
Hello everyone !
I recently design a board based on IMX6Q, with 4G of RAM (DDR3).
I tested my RAM with the NXP ddr test tool V3.0, and found some stange values :
As you can see, I have 3 problems :
- "MPWLHWERR register read out for factory diagnostics"
- "Write DQS0 delay: 0/256 CK" : 0 ????
- DQS gating error calibration
After some research, I found the problem : the CK and CK# has been inverted on the schematic... (it happens sometimes...)
Can I fix this problem without a second PCB batch, via register configuration ? (I'm a student, I can't paid for a second PCB batch...)
Thank you for your help,
Cécile
I recently design a board based on IMX6Q, with 4G of RAM (DDR3).
I tested my RAM with the NXP ddr test tool V3.0, and found some stange values :
Code:
============================================DDR Stress Test (3.0.0)Build: Dec 14 2018, 14:12:06NXP Semiconductors.========================================================================================Chip IDCHIP ID = i.MX6 Dual/Quad (0x63)Internal Revision = TO1.6========================================================================================Boot ConfigurationSRC_SBMR1(0x020d8004) = 0x00002840SRC_SBMR2(0x020d801c) = 0x11000001============================================ARM Clock set to 1GHz============================================DDR configurationBOOT_CFG3[5-4]: 0x00, Single DDR channel.DDR type is DDR3Data width: 64, bank num: 8Row size: 14, col size: 10Chip select CSD0 is usedDensity per chip select: 1024MB============================================Current Temperature: 48============================================DDR Freq: 352 MHzddr_mr1=0x00000000Start write leveling calibration...running Write level HW calibrationMPWLHWERR register read out for factory diagnostics:MPWLHWERR PHY0 = 0x87c38387MPWLHWERR PHY1 = 0xe1c1c3c3Write leveling calibration completed, update the following registers in your initialization scriptMMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x01460000MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x0000013FMMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x012B0136MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x011F0123Write DQS delay result:Write DQS0 delay: 0/256 CKWrite DQS1 delay: 198/256 CKWrite DQS2 delay: 191/256 CKWrite DQS3 delay: 0/256 CKWrite DQS4 delay: 182/256 CKWrite DQS5 delay: 171/256 CKWrite DQS6 delay: 163/256 CKWrite DQS7 delay: 159/256 CKStarting DQS gating calibration. HC_DEL=0x00000000 result[00]=0x11111111. HC_DEL=0x00000001 result[01]=0x11111111. HC_DEL=0x00000002 result[02]=0x11111111. HC_DEL=0x00000003 result[03]=0x11111111. HC_DEL=0x00000004 result[04]=0x11111111. HC_DEL=0x00000005 result[05]=0x11111111. HC_DEL=0x00000006 result[06]=0x11111111. HC_DEL=0x00000007 result[07]=0x11111111. HC_DEL=0x00000008 result[08]=0x11111111. HC_DEL=0x00000009 result[09]=0x11111111. HC_DEL=0x0000000A result[0A]=0x11111111. HC_DEL=0x0000000B result[0B]=0x11111111. HC_DEL=0x0000000C result[0C]=0x11111111. HC_DEL=0x0000000D result[0D]=0x11111111ERROR FOUND, we can't get suitable value !!!!dram test fails for all values.Error: failed during ddr calibration
As you can see, I have 3 problems :
- "MPWLHWERR register read out for factory diagnostics"
- "Write DQS0 delay: 0/256 CK" : 0 ????
- DQS gating error calibration
After some research, I found the problem : the CK and CK# has been inverted on the schematic... (it happens sometimes...)
Can I fix this problem without a second PCB batch, via register configuration ? (I'm a student, I can't paid for a second PCB batch...)
Thank you for your help,
Cécile
robertferanec , 11-12-2022, 03:32 AM
Some systems make it possible do not use differential clock ... I am not sure if this can be setup in iMX6, but maybe try to search if this could be possible and if that could help (?).
Other option could be cut the traces and use wires to swap them (if tracks are exposed). Not the best solution, but could work and could confirm if that fixes the problem. Of course, that could influence the performance, but from my experience, there is still a big change it could work.
Other option could be cut the traces and use wires to swap them (if tracks are exposed). Not the best solution, but could work and could confirm if that fixes the problem. Of course, that could influence the performance, but from my experience, there is still a big change it could work.
Cécile , 11-12-2022, 09:57 AM
Hello,
thank you for your time.
The MMDC controller don't support single CK, only differential (I read it somewhere in a document).
I don't find any software solution, I will try with straps... Tomorrow !
thank you for your time.
Some systems make it possible do not use differential clock ... I am not sure if this can be setup in iMX6, but maybe try to search if this could be possible and if that could help (?).
Other option could be cut the traces and use wires to swap them (if tracks are exposed). Not the best solution, but could work and could confirm if that fixes the problem. Of course, that could influence the performance, but from my experience, there is still a big change it could work.
robertferanec , 11-14-2022, 01:25 AM
Please, let me know if swapping the signals by using short wires worked. I am curious to know. Thank you.
Cécile , 11-15-2022, 04:35 AM
Hello,
Yes it works ! (strapped with 0.1mm diam cable) I will send some pictures of the straps later.
The DQS delay is now around 31, and all the calibration process is ok.
However, the stress test don't pass, probably a error in a register... I have to work on it.
Thank you,
Cécile
Yes it works ! (strapped with 0.1mm diam cable) I will send some pictures of the straps later.
The DQS delay is now around 31, and all the calibration process is ok.
However, the stress test don't pass, probably a error in a register... I have to work on it.
Thank you,
Cécile
Cécile , 11-15-2022, 10:03 AM
Hello,
below some pictures of the board.
have a nice day,
Cécile
below some pictures of the board.
have a nice day,
Cécile
Cécile , 11-19-2022, 12:05 PM
Hello,
I have another problem...
The stress test don't work every time... For exemple, I load the program, run stress test... and it doesn't work. However, if I retry again, it works perfectly (see below).
Do you have a idea of why it doesn't work every time?
Thank you for your help,
Cécile
I have another problem...
The stress test don't work every time... For exemple, I load the program, run stress test... and it doesn't work. However, if I retry again, it works perfectly (see below).
Do you have a idea of why it doesn't work every time?
Thank you for your help,
Cécile
Code:
============================================ DDR Stress Test (3.0.0) Build: Dec 14 2018, 14:12:06 NXP Semiconductors.======================================================================================== Chip IDCHIP ID = i.MX6 Dual/Quad (0x63)Internal Revision = TO1.6======================================================================================== Boot ConfigurationSRC_SBMR1(0x020d8004) = 0x00002840SRC_SBMR2(0x020d801c) = 0x11000001============================================ARM Clock set to 1GHz============================================ DDR configurationBOOT_CFG3[5-4]: 0x00, Single DDR channel.DDR type is DDR3Data width: 64, bank num: 8Row size: 14, col size: 10Chip select CSD0 is usedDensity per chip select: 1024MB============================================DDR Stress Test Iteration 1Current Temperature: 57============================================DDR Freq: 396 MHzt0.1: data is addr testt0: memcpy10 SSN x64 testt1: memcpy8 SSN x64 testt2: byte-wise SSN x64 testt3: memcpy11 random pattern testt4: IRAM_to_DDRv2 testt5: IRAM_to_DDRv1 testt6: read noise walking ones and zeros testDDR Freq: 413 MHzt0.1: data is addr testt0: memcpy10 SSN x64 testt1: memcpy8 SSN x64 testt2: byte-wise SSN x64 testt3: memcpy11 random pattern testt4: IRAM_to_DDRv2 testt5: IRAM_to_DDRv1 testt6: read noise walking ones and zeros testDDR Freq: 432 MHzt0.1: data is addr testt0: memcpy10 SSN x64 testt1: memcpy8 SSN x64 testt2: byte-wise SSN x64 testt3: memcpy11 random pattern testt4: IRAM_to_DDRv2 testt5: IRAM_to_DDRv1 testt6: read noise walking ones and zeros testDDR Freq: 452 MHzt0.1: data is addr testt0: memcpy10 SSN x64 testt1: memcpy8 SSN x64 testt2: byte-wise SSN x64 testt3: memcpy11 random pattern testt4: IRAM_to_DDRv2 testt5: IRAM_to_DDRv1 testt6: read noise walking ones and zeros testDDR Freq: 475 MHzt0.1: data is addr testt0: memcpy10 SSN x64 testt1: memcpy8 SSN x64 testt2: byte-wise SSN x64 testt3: memcpy11 random pattern testt4: IRAM_to_DDRv2 testt5: IRAM_to_DDRv1 testt6: read noise walking ones and zeros testDDR Freq: 500 MHzt0.1: data is addr testt0: memcpy10 SSN x64 testt1: memcpy8 SSN x64 testt2: byte-wise SSN x64 testt3: memcpy11 random pattern testt4: IRAM_to_DDRv2 testt5: IRAM_to_DDRv1 testt6: read noise walking ones and zeros testSuccess: DDR Stress test completed!!!
robertferanec , 11-21-2022, 12:51 AM
What does it mean "doesn't work"? Are there errors or it doesn't start? The board crashes, freezes?
Cécile , 11-22-2022, 10:17 AM
Hello,
Excuse me for the previous post.
After additional tests : the error is (during data is addr test) : "addr : 0x10000000 data was 0x10000008" (I will send logs later, I'm not at home...). The error is already the same... And only appears for frequencies below 400MHz. For 400 to 500MHz stress test, everything is fine (despite the straps).
Thank you,
Cécile
Excuse me for the previous post.
After additional tests : the error is (during data is addr test) : "addr : 0x10000000 data was 0x10000008" (I will send logs later, I'm not at home...). The error is already the same... And only appears for frequencies below 400MHz. For 400 to 500MHz stress test, everything is fine (despite the straps).
Thank you,
Cécile
robertferanec , 11-23-2022, 06:36 AM
try to double check in the memory chip datasheet, what is the recommended lowest frequency ... just in case (it may say something like: Clock frequency range of XXX–YYYMHz).
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