FEDEVEL
Platform forum

mulfycrowh , 01-06-2023, 11:13 AM

Hi everyone,

Before entering production for a motherboard, I would like to compute the insertion loss at Nyquist frequency (8 GHz - PCIe 4) for the root complex between CPU and MXM board.
It is important because I would eventually have to use a redriver or a retimer if the loss is greater than 28dB.

Did you already use a piece of software to do that?

Thanks a lot!

robertferanec , 01-10-2023, 09:22 AM

I talked to someone about this - someone from a company designing high speed connectors. I don't remember what software they use for this, but if you contact your connector manufacturer, they may recommend something.

mulfycrowh , 01-10-2023, 09:54 AM

In the mean time, I found this very interesting article sharing insertion loss for 16 inch PCIe lanes:
Getting Ready for 32 GT/s PCIe 5.0 Designs (semiengineering.com)​

We see that choosing the right material is very important.
FR4 is not the good option for PCIe lanes.
Megtron6 or Tachyon are among the best ones with very low insertion loss.

In my case, the distance between CEX module and MXM board is smaller than 11inch.
If I select Megtron6 (TI's advice), I am far much below 28dB, meaning I don't need any redriver or redriver.

binayak , 01-16-2023, 07:27 PM

If you have the board file, you can use Hyperlynx boardsim (along with 3D simulation at vias, connectors, etc.) to generate and plot S-parameters. You can also use ADS SiPro for the same.