Global decoupling
tuv0k , 11-08-2015, 03:36 PM
Hi guys,
For CPU board design(mostly BGA packages) on which approach you rely on, global or local decoupling?
For CPU board design(mostly BGA packages) on which approach you rely on, global or local decoupling?
robertferanec , 11-09-2015, 02:06 AM
Number of capacitors and values: I use what is recommended in design guide or used in reference schematic
Placement: small values as close to the pins as possible (usually in the area under the pads), larger values around the BGA, largest values in path of the current flow.
Placement: small values as close to the pins as possible (usually in the area under the pads), larger values around the BGA, largest values in path of the current flow.
tuv0k , 11-09-2015, 09:00 AM
What do you think about keeping interplane capacitance evenly distributed along whole board? I've seen couple of EMC guys doing it that way and claiming there is no difference if distance between GND and VDD plane is greater than 0.5mm...
robertferanec , 11-09-2015, 09:01 AM
Do you have a link to an article about it?
tuv0k , 11-09-2015, 09:26 AM
http://electronics.stackexchange.com.../134978#134978
This guy holds a lot of EMC/SI instruction around the world. With good low impedance on the whole board you can safely switch routing layers even on 4 layer board and be confident that there won't be ground loops.
On the other hand, Henry Ott in his book claims that the best way is to place capacitance near the crossing via, but you need to know signal frequency first so you can dimension capacitor properly. I will add few thoughts about that on this post if I find them somewhere.
ADD#1:
"The location of the decoupling capacitors is not critical because their performance is dominated by the inductance of their connection to the planes. At the frequencies where they are effective, they can be located anywhere within the general vicinity of the active devices [1]."
http://learnemc.com/decoupling-for-b...s-power-planes
http://learnemc.com/decoupling-for-b...-spaced-planes
This guy holds a lot of EMC/SI instruction around the world. With good low impedance on the whole board you can safely switch routing layers even on 4 layer board and be confident that there won't be ground loops.
On the other hand, Henry Ott in his book claims that the best way is to place capacitance near the crossing via, but you need to know signal frequency first so you can dimension capacitor properly. I will add few thoughts about that on this post if I find them somewhere.
ADD#1:
"The location of the decoupling capacitors is not critical because their performance is dominated by the inductance of their connection to the planes. At the frequencies where they are effective, they can be located anywhere within the general vicinity of the active devices [1]."
http://learnemc.com/decoupling-for-b...s-power-planes
http://learnemc.com/decoupling-for-b...-spaced-planes
robertferanec , 11-10-2015, 12:18 AM
"The location of the decoupling capacitors is not critical because their performance is dominated by the inductance of their connection to the planes. At the frequencies where they are effective, they can be located anywhere within the general vicinity of the active devices [1]."
I am still not 100% sure what do you mean by "keeping interplane capacitance evenly distributed along whole board", but if possible I try to have a solid GND plane placed as a neighbour layer of a solid power plane (e.g. 3V3). I read in some articles, that it creates a capacitor which may help filter the power.
tuv0k , 11-10-2015, 04:08 PM
You most certainly won't have issues if you place decoupling capacitors near pins, it can't harm. But if IC's on board are 100MHz or more, there is no need to do it that way. However, I agree with you, I will also choose safe option - decoupling near pin with keeping in mind about layer capacitance.
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