DDR2 SDRAM Address Bus Routing Guide line
mohsin_qau , 06-06-2017, 01:15 AM
Dear Sir,
I am designing FPGA card using Alter Cyclone III and DDR II SDRAM. I plan to use Class I parallel termination with series CAL resistor scheme. I am using Vtt resistors with Address/Command Signals only ( Not with DQ and DQS). I make placement as seen in the fig attached.
Firstly, I am routing between Rtt and DDR II SDRAM in the mid (L2) layer.But i have constraints to route between DDR II and FPGA in the same mid (L2) layer. As i have learnt from lecture that Address/CMD signals must be routed on same critical layer. My question is that Is it possible to complete the routing in the two adj cant layers?
Kindly, respond me on urgent basis. i am stuck in that point.
Regards,
Mohsin Hayat
I am designing FPGA card using Alter Cyclone III and DDR II SDRAM. I plan to use Class I parallel termination with series CAL resistor scheme. I am using Vtt resistors with Address/Command Signals only ( Not with DQ and DQS). I make placement as seen in the fig attached.
Firstly, I am routing between Rtt and DDR II SDRAM in the mid (L2) layer.But i have constraints to route between DDR II and FPGA in the same mid (L2) layer. As i have learnt from lecture that Address/CMD signals must be routed on same critical layer. My question is that Is it possible to complete the routing in the two adj cant layers?
Kindly, respond me on urgent basis. i am stuck in that point.
Regards,
Mohsin Hayat
robertferanec , 06-09-2017, 01:16 PM
@mohsin_qau, I am not really sure what you mean by "two adj cant layers"
mohsin_qau , 06-13-2017, 07:02 AM
Respected Sir,
I mean that if i select the Layer "L4" for address bus. But because of termination resistors and to avoid the routing complexity, Would i split the address bus routing between Layer L4 and L5?
Phase 1:
Layer L4: Routing the signals between Termination Resistors and DDR II Memory
Phase 2:
Layer L5: Routing the signals between DDR II and FPGA.
As i am using Fly By Topology with Parallel Termination Class I with series calibration.
Regards,
Mohsin
I mean that if i select the Layer "L4" for address bus. But because of termination resistors and to avoid the routing complexity, Would i split the address bus routing between Layer L4 and L5?
Phase 1:
Layer L4: Routing the signals between Termination Resistors and DDR II Memory
Phase 2:
Layer L5: Routing the signals between DDR II and FPGA.
As i am using Fly By Topology with Parallel Termination Class I with series calibration.
Regards,
Mohsin
robertferanec , 06-14-2017, 12:50 AM
We sometimes route termination on different layer. It looks like, that you are connecting 1 memory chip only, so, it may be fine.
If you are not sure, I always recommend simulation e.g. have a look at Hyperlynx simulator.
If you are not sure, I always recommend simulation e.g. have a look at Hyperlynx simulator.
mohsin_qau , 06-14-2017, 05:47 AM
Its clear to me and i become more confident with your answer.Yes, sure i will do post simulation at the end of completion.
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