Why doesn't use PCIE Gen 1 recommendation in Rex boards ?
Kulunu , 10-08-2018, 10:32 PM
Hi All,
When I go through in Hardware design check list I could see following. (NXP PCIE recommendation) / (Look NXP PCIE recommendation pic)
But when we refer open Rex we can't see those changes. It should be both 470 Ohms and 56 Ohms pull up and pull down resistors for PCIE REFCLK. (open Rex PCIE)
1) Could you please explain why open Rex is not using those changes ?
2) Why we use both pull up and pull down as described in NXP doc ?
Regards,
Kulunu.
When I go through in Hardware design check list I could see following. (NXP PCIE recommendation) / (Look NXP PCIE recommendation pic)
But when we refer open Rex we can't see those changes. It should be both 470 Ohms and 56 Ohms pull up and pull down resistors for PCIE REFCLK. (open Rex PCIE)
1) Could you please explain why open Rex is not using those changes ?
2) Why we use both pull up and pull down as described in NXP doc ?
Regards,
Kulunu.
robertferanec , 10-10-2018, 02:59 AM
Can you attach links to the documentation you are referring to? The chip manufacturers sometimes make adjustments in reference schematic after some time - I could compare it with the documents which we used.
Kulunu , 10-10-2018, 10:40 PM
Hi Robert
Here I have attached NXP hardware design checking list. Look schematic tab in excel sheet and look PCIe-II section and there you can see following comments.
"Due to CLKx_P/N is LVDS port and don't match with PCIe reference clock specification. For PCIe Gen1 application, following low cost soultion can be used(DC bias and AC impedance should be considered). Please click "Ref12" for more info."
Then refer Ref12 picture.
Waiting for your feedback.
I couldn't attach exel doc here. You can get it form this link >> https://community.nxp.com/docs/DOC-93819
Regards,
Kulunu
Here I have attached NXP hardware design checking list. Look schematic tab in excel sheet and look PCIe-II section and there you can see following comments.
"Due to CLKx_P/N is LVDS port and don't match with PCIe reference clock specification. For PCIe Gen1 application, following low cost soultion can be used(DC bias and AC impedance should be considered). Please click "Ref12" for more info."
Then refer Ref12 picture.
Waiting for your feedback.
I couldn't attach exel doc here. You can get it form this link >> https://community.nxp.com/docs/DOC-93819
Regards,
Kulunu
robertferanec , 10-11-2018, 06:37 AM
It was probably added later. I see, that in some revision they added external clock chip. Maybe there really was a problem with the CLOCK(?)
This is the original reference schematic from Freescale:
This is the original reference schematic from Freescale:
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