FEDEVEL
Platform forum

Sonu , 08-12-2024, 08:47 AM

Hey everyone specially @Robert Feranec My problem statement is that I want to establish the connection between client and Server via Verilog and run on linux machine or putty via ssh . I am using alveo u50 FPGA .The state machine is given on Wikipedia if anyone have solution regarding this kindly provide . I must be thankful to you.
With respect
SONU Tripathi
FPGA Engineer

Robert Feranec , 08-12-2024, 08:49 AM

did you watch my latest video with Stacey? Maybe it can help? https://youtu.be/78tkdc6Lq_8

Sonu , 08-12-2024, 08:50 AM

yes I watched this but process not involves in verilog like the client and server model may be developed using python in this video. is any refernce to verilog?

Sonu , 08-12-2024, 08:52 AM

Also I am using PCIE gen express 16 associated to Alveo u50 FPGA.

Robert Feranec , 08-12-2024, 08:53 AM

Than I dont know, maybe someone else can help. Personally I would probably use ZYNQ, but I am not expert for FPGA and also I guess you have reasons why to use alveo

Sonu , 08-12-2024, 08:55 AM

I am using alveo u50 because it mainly develop for data centric appications like HFT. okk is any refernce to client and server connection using verilog?

QDrives , 08-12-2024, 09:06 PM

So is the FPGA running Linux?
Is the FPGA the server or the client?

Google search "TCPIP stack FPGA" first result was: https://github.com/fpgasystems/fpga-network-stack

Sonu , 08-13-2024, 10:43 AM

like for tcp connection management there are three way handshake is any material reference for this?

QDrives , 08-13-2024, 07:19 PM

Do note that most designers that use TCP IP use a stack or IP with everything in it. So few know how to do the handshake.