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Skoomadentist , 06-10-2026, 06:28 PM

Are there downsides to slowing excessively fast digital signals with an RC filter when the driver's slowest rise time is still only a few nanoseconds?
Say I have a mixed signal circuit with an STM32H7 (very fast IOs even at lowest drive level). I'm driving some auxiliary circuit that only requires 200 ns rise time but the slowest speed of STM32H7 is around 5-10 ns and I want to minimize crosstalk to any nearby sensitive analog lines. Can I simply put a 470 ohms / 100 pF RC filter right at the driving pin to slow it down to ~100 ns without risking some unforeseen problems?

, 06-10-2026, 06:33 PM

🤖 In the meantime, here’s a response from the [FEDEVEL AI HW Assistant]().
It helps to find relevant resources for your question, but it may make mistakes as it’s still in early development.

This is the response from the AI Assistant:
Yes, using an RC filter to slow down digital edges is a valid strategy to reduce crosstalk, but requires careful implementation. Here's the breakdown:

**Key Insight:**
Crosstalk depends primarily on edge speed (dV/dt), not signal frequency. Slowing edges from 5-10ns to 100ns could reduce coupled noise by ~10-20x (since crosstalk scales with edge speed). This approach is mentioned in multiple videos showing how edge control impacts noise coupling [Video 1](https://www.youtube.com/watch?v=M0Pn7cKLzXQ&t=1), [Video 2](https://www.youtube.com/watch?v=UbQjOApEe3k&t=1).

**Your Proposed Solution:**
A 470Ω + 100pF filter (τ=47ns) would create ~100ns rise time (≈2.2τ). This aligns with your 200ns peripheral requirement. However:

1. **Driver Loading:**
STM32H7 GPIOs have finite output impedance (~25-50Ω). With 470Ω series R + 100pF load, you'll get voltage division. At 3.3V:
Final voltage = 3.3V * (470Ω)/(470Ω + GPIO_impedance). This might not reach valid logic levels.

2. **Better Alternative:**
Use smaller R + larger C (e.g., 100Ω + 470pF gives similar τ but better voltage transfer). Series resistors <100Ω are safer for digital drivers while still providing edge control [Video 3](https://www.youtube.com/watch?v=UbQjOApEe3k&t=186).

3. **Layout Criticality:**
Place the filter **immediately at the driver pin** - any trace length between GPIO and filter becomes an antenna.

, 06-10-2026, 06:33 PM

Keep analog traces ≥5× digital trace width away (3W rule) [Video 4](https://www.youtube.com/watch?v=LDe3ZJ16HxQ&t=460).

**Unexpected Issues to Watch:**
- **Ground Bounce:** Fast edges filtered at source reduce simultaneous switching noise
- **Reflections:** If trace length > 1/6λ of filtered edge (100ns ≈ 10MHz → 5m!), impedance matching becomes irrelevant
- **Leakage Current:** Large capacitors (100pF+) on multiple lines increase power-on surge currents

**Verification Tip:**
Simulate with IBIS models (STM32H7) + peripheral input characteristics. Measure actual rise time with 10x probe (minimize probe capacitance!). For mixed-signal boards, 100-200ns edges are generally safe if analog sections have proper ground separation and filtering [Video 5](https://www.youtube.com/watch?v=61Qg6zeQvZ8&t=5000).

You can continue chatting with the AI Assistant here:
https://fedevel.com/hw-assistant

Robert Feranec , 06-11-2026, 05:48 AM

using series termination resistors (often 22OHM to 50OHM) to slow down the signal is very standard. in some circuits I have also seen an additional capacitor to slow down the signal even more - but often this capacitor may be there for testing or debugging and maybe not even fit in the final circuit. So you can try to put it there and play with it, in the worst case you still can use 0R and not fit the cap to get the original connections.

Skoomadentist , 06-12-2026, 07:47 PM

Wouldn't a 22 to 50 ohm resistor be purely in the realm of matching to the transmission line impedance? They're far too small to have any meaningful effect at speeds below those at which you have to start caring about impedance matching. Eg. 50 ohms into 50 pF parasitic capacitance results in 2.5 ns time constant, ie. 375 mm propagation distance. One sixth of that is ~60 mm and anything longer that you need to consider the trace as a transmission line if the rise time is indeed 2.5 ns.

Robert Feranec , 06-13-2026, 07:28 AM

good point

QDrives , 06-16-2026, 02:51 PM

So what is stopping you from placing a 1kΩ resistor in series?
What is the load impedance?

Skoomadentist , 06-16-2026, 10:27 PM

1k resistor by itself wouldn’t necessarily help much either as any slowdown would depend on the trace and pin parasitic capacitances. 1k resistor and a small cap should being that under control.
The load is a bog standard cmos analog mux control input,

Skoomadentist , 06-16-2026, 10:32 PM

The timing has around 500 ns slack in each direction, so a 200 ns rise / fall time would still have over 100% safety margin.

QDrives , 06-17-2026, 04:00 PM

What makes you think a resistor does not help?

QDrives , 06-17-2026, 04:03 PM

Green is 1Ω (+20Ω output impedance).
Blue is 30Ω series termination.
Red is 1kΩ series termination.
All on the 50Ω transmission line.
Top is using the lossless transmission line model.
The bottom in lumped elements.

Skoomadentist , 06-17-2026, 04:44 PM

It helps a bit but not nearly as much as I’d like because the parasitic capacitance is perhaps 30 pF which is small compared to 100 pF + 30 pF capacitance that adding extra capacitor produced. Or to put it another way, explicitly adding that capacitor reduces rise time to one fourth compared to just a resistor.

QDrives , 06-17-2026, 08:40 PM

With a 1k resistor it does not matter much, but for the low resistance values your current goes up.
But if you want to add a capacitor, go ahead, nothing and nobody is stopping you.
The only downside of a high series resistor is the voltage drop you get.